arm64: dts: renesas: r9a07g044: Add vspd node

Add vspd node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230411100346.299768-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index dd98688c36616024940400f9545b5596a83c33b4..796ad2034699a54cbfa8c8d331fa17c2c86043ce 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -697,6 +697,19 @@
                        };
                };
 
+               vspd: vsp@10870000 {
+                       compatible = "renesas,r9a07g044-vsp2";
+                       reg = <0 0x10870000 0 0x10000>;
+                       interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+                                <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+                                <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A07G044_LCDC_RESET_N>;
+                       renesas,fcp = <&fcpvd>;
+               };
+
                fcpvd: fcp@10880000 {
                        compatible = "renesas,r9a07g044-fcpvd",
                                     "renesas,fcpv";