BCM2711_DMA40_BURST_LEN(BCM2835_DMA_GET_BURST_LENGTH(info));
}
-static inline uint32_t to_bcm2711_cbaddr(dma_addr_t addr)
+static inline uint32_t to_40bit_cbaddr(dma_addr_t addr)
{
BUG_ON(addr & 0x1f);
return (addr >> 5);
if (frame && c->is_40bit_channel)
((struct bcm2711_dma40_scb *)
d->cb_list[frame - 1].cb)->next_cb =
- to_bcm2711_cbaddr(cb_entry->paddr);
+ to_40bit_cbaddr(cb_entry->paddr);
if (frame && !c->is_40bit_channel)
- d->cb_list[frame - 1].cb->next = to_bcm2711_cbaddr(cb_entry->paddr);
+ d->cb_list[frame - 1].cb->next = to_40bit_cbaddr(cb_entry->paddr);
/* update src and dst and length */
if (src && (info & BCM2835_DMA_S_INC)) {
c->desc = d = to_bcm2835_dma_desc(&vd->tx);
if (c->is_40bit_channel) {
- writel(to_bcm2711_cbaddr(d->cb_list[0].paddr),
+ writel(to_40bit_cbaddr(d->cb_list[0].paddr),
c->chan_base + BCM2711_DMA40_CB);
writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAGS(c->dreq),
c->chan_base + BCM2711_DMA40_CS);
} else {
writel(BIT(31), c->chan_base + BCM2835_DMA_CS);
- writel(to_bcm2711_cbaddr(d->cb_list[0].paddr),
+ writel(to_40bit_cbaddr(d->cb_list[0].paddr),
c->chan_base + BCM2835_DMA_ADDR);
writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
c->chan_base + BCM2835_DMA_CS);
if (c->is_40bit_channel)
((struct bcm2711_dma40_scb *)
d->cb_list[frames - 1].cb)->next_cb =
- to_bcm2711_cbaddr(d->cb_list[0].paddr);
+ to_40bit_cbaddr(d->cb_list[0].paddr);
else
- d->cb_list[d->frames - 1].cb->next = to_bcm2711_cbaddr(d->cb_list[0].paddr);
+ d->cb_list[d->frames - 1].cb->next = to_40bit_cbaddr(d->cb_list[0].paddr);
return vchan_tx_prep(&c->vc, &d->vd, flags);
}
scb->len = size;
scb->next_cb = 0;
- writel(to_bcm2711_cbaddr(memcpy_scb_dma), memcpy_chan + BCM2711_DMA40_CB);
+ writel(to_40bit_cbaddr(memcpy_scb_dma), memcpy_chan + BCM2711_DMA40_CB);
writel(BCM2711_DMA40_MEMCPY_FLAGS | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT,
memcpy_chan + BCM2711_DMA40_CS);