drm/bridge: tc358767: fix single lane configuration

[ Upstream commit 4d9d54a730434cc068dd3515ba6116697196f77b ]

PHY_2LANE bit is always set in DP_PHY_CTRL, breaking 1 lane use.

Set PHY_2LANE only when 2 lanes are used.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-4-tomi.valkeinen@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 5f0a666..fee5342 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -543,6 +543,7 @@ static int tc_aux_link_setup(struct tc_data *tc)
        unsigned long rate;
        u32 value;
        int ret;
+       u32 dp_phy_ctrl;
 
        rate = clk_get_rate(tc->refclk);
        switch (rate) {
@@ -567,7 +568,10 @@ static int tc_aux_link_setup(struct tc_data *tc)
        value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
        tc_write(SYS_PLLPARAM, value);
 
-       tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN);
+       dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
+       if (tc->link.base.num_lanes == 2)
+               dp_phy_ctrl |= PHY_2LANE;
+       tc_write(DP_PHY_CTRL, dp_phy_ctrl);
 
        /*
         * Initially PLLs are in bypass. Force PLL parameter update,
@@ -860,7 +864,9 @@ static int tc_main_link_setup(struct tc_data *tc)
        tc_write(SYS_PLLPARAM, value);
 
        /* Setup Main Link */
-       dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN |  PHY_M0_EN;
+       dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
+       if (tc->link.base.num_lanes == 2)
+               dp_phy_ctrl |= PHY_2LANE;
        tc_write(DP_PHY_CTRL, dp_phy_ctrl);
        msleep(100);