drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid

Enable FW DSTATE for sienna_cichlid.
Enable DF CSTATE for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 49e157f2b39fdeed6be163351503208e978a4fbf..a91e6f753bea36e9b4c31b594322cbd8a14290dc 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -272,6 +272,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
                                | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
                                | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+                               | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
+                               | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
                                | FEATURE_MASK(FEATURE_THERMAL_BIT);
 
        if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)