KVM: vmx/pmu: Release guest LBR event via lazy release mechanism

The vPMU uses GUEST_LBR_IN_USE_IDX (bit 58) in 'pmu->pmc_in_use' to
indicate whether a guest LBR event is still needed by the vcpu. If the
vcpu no longer accesses LBR related registers within a scheduling time
slice, and the enable bit of LBR has been unset, vPMU will treat the
guest LBR event as a bland event of a vPMC counter and release it
as usual. Also, the pass-through state of LBR records msrs is cancelled.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20210201051039.255478-10-like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 405890c723a1bf7081df4314a736ce27e739403d..136dc2f3c5d318741115e4412fc05224610c120d 100644 (file)
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -476,6 +476,9 @@ void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
                        pmc_stop_counter(pmc);
        }
 
+       if (kvm_x86_ops.pmu_ops->cleanup)
+               kvm_x86_ops.pmu_ops->cleanup(vcpu);
+
        bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);
 }
 

diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index 742a4e98df8c7218a9afce967e8462f58805e3e1..7b30bc967af38c2da2781cba6dbb0d1fb906ff15 100644 (file)
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -40,6 +40,7 @@ struct kvm_pmu_ops {
        void (*init)(struct kvm_vcpu *vcpu);
        void (*reset)(struct kvm_vcpu *vcpu);
        void (*deliver_pmi)(struct kvm_vcpu *vcpu);
+       void (*cleanup)(struct kvm_vcpu *vcpu);
 };
 
 static inline u64 pmc_bitmask(struct kvm_pmc *pmc)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 7928d6dee0a26de6cc3b342df78dc1727d2c7d3b..d1df618cb7deb47e535c5686b5860bc014405ab1 100644 (file)
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -288,8 +288,10 @@ int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu)
                                        PERF_SAMPLE_BRANCH_USER,
        };
 
-       if (unlikely(lbr_desc->event))
+       if (unlikely(lbr_desc->event)) {
+               __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
                return 0;
+       }
 
        event = perf_event_create_kernel_counter(&attr, -1,
                                                current, NULL, NULL);
@@ -300,6 +302,7 @@ int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu)
        }
        lbr_desc->event = event;
        pmu->event_count++;
+       __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
        return 0;
 }
 
@@ -332,9 +335,11 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
                        rdmsrl(index, msr_info->data);
                else
                        wrmsrl(index, msr_info->data);
+               __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
                local_irq_enable();
                return true;
        }
+       clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
        local_irq_enable();
 
 dummy:
@@ -532,6 +537,9 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
                x86_perf_get_lbr(&lbr_desc->records);
        else
                lbr_desc->records.nr = 0;
+
+       if (lbr_desc->records.nr)
+               bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1);
 }
 
 static void intel_pmu_init(struct kvm_vcpu *vcpu)
@@ -665,17 +673,21 @@ static inline void vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu)
  */
 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu)
 {
+       struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
        struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
 
        if (!lbr_desc->event) {
                vmx_disable_lbr_msrs_passthrough(vcpu);
                if (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR)
                        goto warn;
+               if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use))
+                       goto warn;
                return;
        }
 
        if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) {
                vmx_disable_lbr_msrs_passthrough(vcpu);
+               __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
                goto warn;
        } else
                vmx_enable_lbr_msrs_passthrough(vcpu);
@@ -687,6 +699,12 @@ warn:
                vcpu->vcpu_id);
 }
 
+static void intel_pmu_cleanup(struct kvm_vcpu *vcpu)
+{
+       if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR))
+               intel_pmu_release_guest_lbr_event(vcpu);
+}
+
 struct kvm_pmu_ops intel_pmu_ops = {
        .find_arch_event = intel_find_arch_event,
        .find_fixed_event = intel_find_fixed_event,
@@ -702,4 +720,5 @@ struct kvm_pmu_ops intel_pmu_ops = {
        .init = intel_pmu_init,
        .reset = intel_pmu_reset,
        .deliver_pmi = intel_pmu_deliver_pmi,
+       .cleanup = intel_pmu_cleanup,
 };