Ampere.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
}
}
-static void
-gf100_gr_intr(struct nvkm_gr *base)
+static irqreturn_t
+gf100_gr_intr(struct nvkm_inth *inth)
{
- struct gf100_gr *gr = gf100_gr(base);
+ struct gf100_gr *gr = container_of(inth, typeof(*gr), base.engine.subdev.inth);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_chan *chan;
nvkm_wr32(device, 0x400500, 0x00010001);
nvkm_chan_put(&chan, flags);
+ return IRQ_HANDLED;
}
static void
struct gf100_gr *gr = gf100_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
+ struct nvkm_intr *intr = &device->mc->intr;
+ enum nvkm_intr_type intr_type = NVKM_INTR_SUBDEV;
int ret, i, j;
+ ret = nvkm_inth_add(intr, intr_type, NVKM_INTR_PRIO_NORMAL, &gr->base.engine.subdev,
+ gf100_gr_intr, &gr->base.engine.subdev.inth);
+ if (ret)
+ return ret;
+
nvkm_pmu_pgob(device->pmu, false);
gr->rop_nr = gr->func->rops(gr);
struct nvkm_subdev *subdev = &base->engine.subdev;
struct nvkm_device *device = subdev->device;
bool reset = device->chipset == 0x137 || device->chipset == 0x138;
- u32 ret;
+ int ret;
/* On certain GP107/GP108 boards, we trigger a weird issue where
* GR will stop responding to PRI accesses after we've asked the
if (ret)
return ret;
- return gr->func->init(gr);
+ ret = gr->func->init(gr);
+ if (ret)
+ return ret;
+
+ nvkm_inth_allow(&subdev->inth);
+ return 0;
}
static int
{
struct gf100_gr *gr = gf100_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
+
+ nvkm_inth_block(&subdev->inth);
+
nvkm_falcon_put(&gr->gpccs.falcon, subdev);
nvkm_falcon_put(&gr->fecs.falcon, subdev);
return 0;
.init = gf100_gr_init_,
.fini = gf100_gr_fini,
.reset = gf100_gr_reset,
- .intr = gf100_gr_intr,
.units = gf100_gr_units,
.chan_new = gf100_gr_chan_new,
.object_get = gf100_gr_object_get,
{ NVKM_ENGINE_DISP , 0, 0, 0x04000000, true },
{ NVKM_ENGINE_MSPDEC , 0, 0, 0x00020000, true },
{ NVKM_ENGINE_MSVLD , 0, 0, 0x00008000, true },
- { NVKM_ENGINE_GR , 0, 0, 0x00001000, true },
+ { NVKM_ENGINE_GR , 0, 0, 0x00001000 },
{ NVKM_ENGINE_FIFO , 0, 0, 0x00000100 },
{ NVKM_ENGINE_CE , 1, 0, 0x00000040, true },
{ NVKM_ENGINE_CE , 0, 0, 0x00000020, true },
{ NVKM_SUBDEV_I2C , 0, 0, 0x00200000, true },
{ NVKM_SUBDEV_TIMER , 0, 0, 0x00100000, true },
{ NVKM_SUBDEV_THERM , 0, 0, 0x00040000, true },
- { NVKM_SUBDEV_TOP , 0, 0, 0xffffffff, true },
+ { NVKM_SUBDEV_TOP , 0, 0, 0x00001000 },
+ { NVKM_SUBDEV_TOP , 0, 0, 0xffffefff, true },
{},
};
{ NVKM_SUBDEV_I2C , 0, 0, 0x00200000, true },
{ NVKM_SUBDEV_TIMER , 0, 0, 0x00100000, true },
{ NVKM_SUBDEV_THERM , 0, 0, 0x00040000, true },
- { NVKM_SUBDEV_TOP , 0, 0, 0x00008000 },
- { NVKM_SUBDEV_TOP , 0, 0, 0xffff7fff, true },
+ { NVKM_SUBDEV_TOP , 0, 0, 0x00009000 },
+ { NVKM_SUBDEV_TOP , 0, 0, 0xffff6fff, true },
{},
};