}
/* MSKWH, MSKLH, MSKQH */
-static void gen_msk_h(int ra, int rb, int rc, int islit,
+static void gen_msk_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~((byte_mask << (lit & 7)) >> 8));
+ if (islit) {
+ gen_zapnoti(vc, va, ~((byte_mask << (lit & 7)) >> 8));
} else {
TCGv shift = tcg_temp_new();
TCGv mask = tcg_temp_new();
shift of 64 bits in order to generate a zero. This is done by
splitting the shift into two parts, the variable shift - 1
followed by a constant 1 shift. The code we expand below is
- equivalent to ~((B & 7) * 8) & 63. */
+ equivalent to ~(B * 8) & 63. */
- tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
- tcg_gen_shli_i64(shift, shift, 3);
+ tcg_gen_shli_i64(shift, load_gpr(ctx, rb), 3);
tcg_gen_not_i64(shift, shift);
tcg_gen_andi_i64(shift, shift, 0x3f);
tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));
tcg_gen_shr_i64(mask, mask, shift);
tcg_gen_shri_i64(mask, mask, 1);
- tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);
+ tcg_gen_andc_i64(vc, va, mask);
tcg_temp_free(mask);
tcg_temp_free(shift);
}
/* MSKBL, MSKWL, MSKLL, MSKQL */
-static void gen_msk_l(int ra, int rb, int rc, int islit,
+static void gen_msk_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~(byte_mask << (lit & 7)));
+ if (islit) {
+ gen_zapnoti(vc, va, ~(byte_mask << (lit & 7)));
} else {
TCGv shift = tcg_temp_new();
TCGv mask = tcg_temp_new();
- tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
+ tcg_gen_andi_i64(shift, load_gpr(ctx, rb), 7);
tcg_gen_shli_i64(shift, shift, 3);
- tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));
+ tcg_gen_movi_i64(mask, zapnot_mask(byte_mask));
tcg_gen_shl_i64(mask, mask, shift);
- tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);
+ tcg_gen_andc_i64(vc, va, mask);
tcg_temp_free(mask);
tcg_temp_free(shift);
switch (fn7) {
case 0x02:
/* MSKBL */
- gen_msk_l(ra, rb, rc, islit, lit, 0x01);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x01);
break;
case 0x06:
/* EXTBL */
break;
case 0x12:
/* MSKWL */
- gen_msk_l(ra, rb, rc, islit, lit, 0x03);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x16:
/* EXTWL */
break;
case 0x22:
/* MSKLL */
- gen_msk_l(ra, rb, rc, islit, lit, 0x0f);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x26:
/* EXTLL */
break;
case 0x32:
/* MSKQL */
- gen_msk_l(ra, rb, rc, islit, lit, 0xff);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x34:
/* SRL */
break;
case 0x52:
/* MSKWH */
- gen_msk_h(ra, rb, rc, islit, lit, 0x03);
+ gen_msk_h(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x57:
/* INSWH */
break;
case 0x62:
/* MSKLH */
- gen_msk_h(ra, rb, rc, islit, lit, 0x0f);
+ gen_msk_h(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x67:
/* INSLH */
break;
case 0x72:
/* MSKQH */
- gen_msk_h(ra, rb, rc, islit, lit, 0xff);
+ gen_msk_h(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x77:
/* INSQH */