clk: samsung: exynos850: Add AUD and HSI main gate clocks

Add main gate clocks for controlling AUD and HSI CMUs:
  - gout_aud_cmu_aud_pclk
  - gout_hsi_cmu_hsi_pclk

Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on
boot otherwise.

While at it, add missing PPMU (Performance Profiling Monitor Unit)
clocks for CMU_HSI.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20230223042133.26551-6-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index 601fe05..6ab5fa8 100644 (file)
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4   0x2014
 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5   0x2018
 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6   0x201c
+#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK       0x2020
 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK         0x2048
 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY    0x204c
 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB     0x2050
@@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst = {
        CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
        CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
        CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
+       CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK,
        CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
        CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
        CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
@@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] __initconst = {
 };
 
 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
+       GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk",
+            "dout_aud_busd",
+            CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
             CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
        GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
@@ -1116,12 +1121,15 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER                  0x0610
 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER                  0x0620
 #define CLK_CON_MUX_MUX_CLK_HSI_RTC                            0x1000
+#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK                       0x2000
 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV            0x2008
 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50              0x200c
 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26           0x2010
 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK                     0x2018
 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK                   0x2024
 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN                  0x2028
+#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK                         0x202c
+#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK                         0x2030
 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK                   0x2038
 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20      0x203c
 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY                0x2040
@@ -1131,12 +1139,15 @@ static const unsigned long hsi_clk_regs[] __initconst = {
        PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
        PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
        CLK_CON_MUX_MUX_CLK_HSI_RTC,
+       CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK,
        CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
        CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
        CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
        CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
        CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
        CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
+       CLK_CON_GAT_GOUT_HSI_PPMU_ACLK,
+       CLK_CON_GAT_GOUT_HSI_PPMU_PCLK,
        CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
        CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
        CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
@@ -1162,6 +1173,10 @@ static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
 };
 
 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
+       /* TODO: Should be enabled in corresponding driver */
+       GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk",
+            "mout_hsi_bus_user",
+            CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
             CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
        GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
@@ -1176,6 +1191,10 @@ static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
        GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
             "mout_hsi_mmc_card_user",
             CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user",
+            CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
+       GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user",
+            CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
        GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
             "mout_hsi_bus_user",
             CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),