struct aml_demod_sts demod_sts;
struct aml_demod_sta demod_sta;
int strenth;
-
- int ilock;
+ int ilock = 0;
/*check tuner*/
if (!timer_tuner_not_enough()) {
return 0;
}
}
+
/*demod_sts.ch_sts = qam_read_reg(0x6);*/
demod_sts.ch_sts = dvbc_get_ch_sts();
dvbc_status(&demod_sta, /*&demod_i2c,*/ &demod_sts);
+
if (demod_sts.ch_sts & 0x1) {
ilock = 1;
*status =
timer_disable(D_TIMER_DETECT);
}
}
+
if (last_lock != ilock) {
PR_DBG("%s.\n",
ilock ? "!! >> LOCK << !!" : "!! >> UNLOCK << !!");
return 0;
}
+static int demod_dvbc_speed_up(enum fe_status *status)
+{
+ unsigned int cnt, i, sts, check_ok = 0;
+ struct aml_demod_sts demod_sts;
+ const int dvbc_count = 5;
+ int ilock = 0;
+
+ if (*status == 0) {
+ for (cnt = 0; cnt < 10; cnt++) {
+ demod_sts.ch_sts = dvbc_get_ch_sts();
+
+ if (demod_sts.ch_sts & 0x1) {
+ /*have signal*/
+ *status =
+ FE_HAS_LOCK | FE_HAS_SIGNAL |
+ FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC;
+ ilock = 1;
+ check_ok = 1;
+ } else {
+ for (i = 0; i < dvbc_count; i++) {
+ sts = dvbc_get_status();
+
+ if (sts >= 0x3)
+ break;
+
+ msleep(25);
+ }
+
+ PR_DBG("[rsj]dvbc_status is 0x%x\n", sts);
+
+ if (sts < 0x3) {
+ *status = FE_TIMEDOUT;
+ ilock = 0;
+ check_ok = 1;
+ }
+ }
+
+ if (check_ok == 1)
+ break;
+
+ msleep(20);
+ }
+ }
+
+ if (last_lock != ilock) {
+ PR_DBG("%s : %s.\n", __func__,
+ ilock ? "!! >> LOCK << !!" : "!! >> UNLOCK << !!");
+ last_lock = ilock;
+ }
+
+ return 0;
+}
+
static int gxtv_demod_dvbc_read_ber(struct dvb_frontend *fe, u32 *ber)
{
/*struct aml_fe_dev *dev = afe->dtv_demod;*/
}
/*extern int aml_fe_analog_set_frontend(struct dvb_frontend *fe);*/
-
static int gxtv_demod_dvbc_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
PR_INFO("%s\n", __func__);
/*timer_set_max(D_TIMER_DETECT, 4000);*/
/*timer_begain(D_TIMER_DETECT);*/
-
memset(¶m, 0, sizeof(param));
param.ch_freq = c->frequency / 1000;
param.mode = amdemod_qam(c->modulation);
if (atsc_flag != QAM_AUTO)
atsc_flag = QAM_AUTO;
/* demod_set_demod_reg(0x502, TXLX_ADC_REG6);*/
- if (!is_ic_ver(IC_VER_TL1))
- dd_tvafe_hiu_reg_write(D_HHI_DEMOD_CLK_CNTL, 0x502);
+ //sys_clk=167M
+ dd_tvafe_hiu_reg_write(D_HHI_DEMOD_CLK_CNTL, 0x502);
demod_set_mode_ts(Gxtv_Dvbc);
param_j83b.ch_freq = c->frequency / 1000;
((front_read_reg_v4(0x20) & ~0xff)
| (nco_rate & 0xff)));
front_write_reg_v4(0x2f, 0x5);//for timeshift mosaic
- dd_tvafe_hiu_reg_write(0x1d0, 0x502);//sys_clk=167M
}
dvbc_set_ch(&demod_status, /*&demod_i2c, */¶m_j83b);
set_j83b_filter_reg_v4();
qam_write_reg(0x12, 0x50e1000);
qam_write_reg(0x30, 0x41f2f69);
- //for timeshift mosaic issue
- //qam_write_reg(0x84, 0x2190000);
}
} else if (c->modulation > QAM_AUTO) {
}
}
- if (is_ic_ver(IC_VER_TL1))
- return 0;
-
if ((auto_search_std == 1) && ((c->modulation <= QAM_AUTO)
&& (c->modulation != QPSK))) {
unsigned char s = 0;
for (cnt = 0; cnt < CNT_FIRST; cnt++) {
gxtv_demod_atsc_read_status(fe, &cs);
- if (is_ic_ver(IC_VER_TL1)) {
- *s = cs;
- return 0;
- }
-
if (cs != 0x1f) {
/*msleep(200);*/
PR_DBG("[j.83b] 1\n");
return 0;
}
-#ifdef DVB_CORE_ORI
-
+#ifdef DVB_CORE_ORI
static int gxtv_demod_dvbc_tune(struct dvb_frontend *fe, bool re_tune,
unsigned int mode_flags, unsigned int *delay, enum fe_status *status)
{
*delay = HZ / 4;
-#if 1
if (re_tune) {
/*first*/
dtvdd_devp->en_detect = 1;
timer_begain(D_TIMER_DETECT);
gxtv_demod_dvbc_read_status_timer(fe, status);
+ if (is_ic_ver(IC_VER_TL1))
+ demod_dvbc_speed_up(status);
+
PR_DBG("tune finish!\n");
return ret;
}
-#endif
+
if (!dtvdd_devp->en_detect) {
PR_DBGL("tune:not enable\n");
return ret;
ret = -1;
}
/* if (ret != 0) return ret; */
- demod_sta->dvb_mode = 0;
+ //demod_sta->dvb_mode = 0;
demod_sta->ch_mode = mode;
/* 0:16, 1:32, 2:64, 3:128, 4:256 */
demod_sta->agc_mode = 1;
/* // configure min symbol_rate fb = 6.95M*/
qam_write_reg(0x12, (qam_read_reg(0x12) & ~(0xff<<8)) | 3400 * 256);
+ #if 0
if (is_ic_ver(IC_VER_TL1))
qam_write_reg(0x51, (qam_read_reg(0x51)&~(0x1<<28)));
+ #endif
/* configure min symbol_rate fb = 6.95M */
/*dvbc_write_reg(QAM_BASE+0x0c0, 0xffffff68); // threshold */
/* enable irq */
qam_write_reg(0x34, 0x7fff << 3);
-#if 1
+
/*if (is_meson_txlx_cpu()) {*/
- if (is_ic_ver(IC_VER_TXLX)) {
+ if (is_ic_ver(IC_VER_TXLX) || (is_ic_ver(IC_VER_TL1))) {
/*my_tool setting j83b mode*/
qam_write_reg(0x7, 0x10f33);
- /*j83b filter para*/
- qam_write_reg(0x40, 0x3f010201);
- qam_write_reg(0x41, 0x0a003a3b);
- qam_write_reg(0x42, 0xe1ee030e);
- qam_write_reg(0x43, 0x002601f2);
- qam_write_reg(0x44, 0x009b006b);
- qam_write_reg(0x45, 0xb3a1905);
- qam_write_reg(0x46, 0x1c396e07);
- qam_write_reg(0x47, 0x3801cc08);
- qam_write_reg(0x48, 0x10800a2);
- qam_write_reg(0x12, 0x50e1000);
- qam_write_reg(0x30, 0x41f2f69);
- /*j83b_symbolrate(please see register doc)*/
- qam_write_reg(0x4d, 0x23d125f7);
- /*for phase noise case 256qam*/
- qam_write_reg(0x9c, 0x2a232100);
- qam_write_reg(0x57, 0x606040d);
- /*for phase noise case 64qam*/
- qam_write_reg(0x54, 0x606050d);
- qam_write_reg(0x52, 0x346dc);
+
+ if (demod_sta->dvb_mode == Gxtv_Atsc ||
+ is_ic_ver(IC_VER_TXLX)) {
+ /*j83b filter para*/
+ qam_write_reg(0x40, 0x3f010201);
+ qam_write_reg(0x41, 0x0a003a3b);
+ qam_write_reg(0x42, 0xe1ee030e);
+ qam_write_reg(0x43, 0x002601f2);
+ qam_write_reg(0x44, 0x009b006b);
+ qam_write_reg(0x45, 0xb3a1905);
+ qam_write_reg(0x46, 0x1c396e07);
+ qam_write_reg(0x47, 0x3801cc08);
+ qam_write_reg(0x48, 0x10800a2);
+ qam_write_reg(0x12, 0x50e1000);
+ qam_write_reg(0x30, 0x41f2f69);
+ /*j83b_symbolrate(please see register doc)*/
+ qam_write_reg(0x4d, 0x23d125f7);
+ /*for phase noise case 256qam*/
+ qam_write_reg(0x9c, 0x2a232100);
+ qam_write_reg(0x57, 0x606040d);
+ /*for phase noise case 64qam*/
+ qam_write_reg(0x54, 0x606050d);
+ qam_write_reg(0x52, 0x346dc);
+ }
+
qam_auto_scan(1);
}
-#endif
- if (!is_ic_ver(IC_VER_TL1)) {
- qam_write_reg(0x7, 0x10f23);
- qam_write_reg(0x3a, 0x0);
- qam_write_reg(0x7, 0x10f33);
- qam_write_reg(0x3a, 0x4);
- }
+
+ qam_write_reg(0x7, 0x10f23);
+ qam_write_reg(0x3a, 0x0);
+ qam_write_reg(0x7, 0x10f33);
+ qam_write_reg(0x3a, 0x4);
/*auto track*/
/* dvbc_set_auto_symtrack(); */
}