engine->fifo.save_context = nv10_fifo_save_context;
break;
case 0x40:
+ case 0x60:
engine->instmem.init = nv04_instmem_init;
engine->instmem.takedown= nv04_instmem_takedown;
engine->instmem.populate = nv04_instmem_populate;
ctx_init = nv4b_graph_context_init;
break;
case 0x4c:
+ case 0x67:
ctx_size = NV4C_GRCTX_SIZE;
ctx_init = nv4c_graph_context_init;
break;
case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break;
case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;
case 0x4b: ctx_voodoo = nv49_4b_ctx_voodoo; break;
- case 0x4c: ctx_voodoo = nv4c_ctx_voodoo; break;
+ case 0x4c:
+ case 0x67: ctx_voodoo = nv4c_ctx_voodoo; break;
case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;
default:
DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n",