PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
describe its meaning.

Link: https://lore.kernel.org/r/3025d5e1d8da64798db6958f9780c4763fbcac47.1655799816.git.baruch@tkos.co.il
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index b979592..07f5603 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -69,7 +69,20 @@
 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1                0x81c
 #define CFG_BRIDGE_SB_INIT                     BIT(0)
 
-#define PCIE_CAP_LINK1_VAL                     0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL          FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \
+                                               250)
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE                FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \
+                                               1)
+#define PCIE_CAP_SLOT_VAL                      (PCI_EXP_SLTCAP_ABP | \
+                                               PCI_EXP_SLTCAP_PCP | \
+                                               PCI_EXP_SLTCAP_MRLSP | \
+                                               PCI_EXP_SLTCAP_AIP | \
+                                               PCI_EXP_SLTCAP_PIP | \
+                                               PCI_EXP_SLTCAP_HPS | \
+                                               PCI_EXP_SLTCAP_HPC | \
+                                               PCI_EXP_SLTCAP_EIP | \
+                                               PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+                                               PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
 
 #define PCIE20_PARF_Q2A_FLUSH                  0x1AC
 
@@ -1132,7 +1145,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
 
        writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
        writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-       writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+       writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
        val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
        val &= ~PCI_EXP_LNKCAP_ASPMS;