intel: fix relaxed tiling on gen2

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 3cdffce..9b324d9 100644 (file)
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -744,7 +744,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
        uint32_t tiling;
 
        do {
-               unsigned long aligned_y;
+               unsigned long aligned_y, height_alignment;
 
                tiling = *tiling_mode;
 
@@ -760,12 +760,16 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
                 * too so we try to be careful.
                 */
                aligned_y = y;
-               if (tiling == I915_TILING_NONE)
-                       aligned_y = ALIGN(y, 2);
-               else if (tiling == I915_TILING_X)
-                       aligned_y = ALIGN(y, 8);
+               height_alignment = 2;
+
+               if (tiling == I915_TILING_X)
+                       height_alignment = 8;
                else if (tiling == I915_TILING_Y)
-                       aligned_y = ALIGN(y, 32);
+                       height_alignment = 32;
+               /* i8xx has a interleaved 2-row tile layout */
+               if (IS_GEN2(bufmgr_gem))
+                       height_alignment *= 2;
+               aligned_y = ALIGN(y, height_alignment);
 
                stride = x * cpp;
                stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);