arm64: dts: renesas: r9a07g043: Add ADC node

Add ADC node to R9A07G043 (RZ/G2UL) SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220505184353.512133-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index b31fb71..40201a1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -483,8 +483,27 @@
                };
 
                adc: adc@10059000 {
+                       compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
                        reg = <0 0x10059000 0 0x400>;
-                       /* place holder */
+                       interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
+                                <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
+                       clock-names = "adclk", "pclk";
+                       resets = <&cpg R9A07G043_ADC_PRESETN>,
+                                <&cpg R9A07G043_ADC_ADRST_N>;
+                       reset-names = "presetn", "adrst-n";
+                       power-domains = <&cpg>;
+                       status = "disabled";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       channel@0 {
+                               reg = <0>;
+                       };
+                       channel@1 {
+                               reg = <1>;
+                       };
                };
 
                tsu: thermal@10059400 {