drm/msm/dpu: correct MERGE_3D length
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tue, 13 Jun 2023 00:09:41 +0000 (03:09 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fri, 16 Jun 2023 09:43:24 +0000 (12:43 +0300)
Each MERGE_3D block has just two registers. Correct the block length
accordingly.

Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/542177/
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20230613001004.3426676-3-dmitry.baryshkov@linaro.org
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

index 36ba3f5..0de507d 100644 (file)
@@ -508,7 +508,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
 #define MERGE_3D_BLK(_name, _id, _base) \
        {\
        .name = _name, .id = _id, \
-       .base = _base, .len = 0x100, \
+       .base = _base, .len = 0x8, \
        .features = MERGE_3D_SM8150_MASK, \
        .sblk = NULL \
        }