net: enetc: use common naming scheme for PTGCR and PTGCAPR registers

The Port Time Gating Control Register (PTGCR) and Port Time Gating
Capability Register (PTGCAPR) have definitions in the driver which
aren't in line with the other registers. Rename these.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index 0b85e37a00ebd54cfa907d3aa504b34df2ff9bcf..18ca1f42b1f754584dbab8471e16f31e68ee9836 100644 (file)
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
@@ -945,13 +945,13 @@ static inline u32 enetc_usecs_to_cycles(u32 usecs)
 }
 
 /* port time gating control register */
-#define ENETC_QBV_PTGCR_OFFSET         0x11a00
-#define ENETC_QBV_TGE                  BIT(31)
-#define ENETC_QBV_TGPE                 BIT(30)
+#define ENETC_PTGCR                    0x11a00
+#define ENETC_PTGCR_TGE                        BIT(31)
+#define ENETC_PTGCR_TGPE               BIT(30)
 
 /* Port time gating capability register */
-#define ENETC_QBV_PTGCAPR_OFFSET       0x11a08
-#define ENETC_QBV_MAX_GCL_LEN_MASK     GENMASK(15, 0)
+#define ENETC_PTGCAPR                  0x11a08
+#define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)
 
 /* Port time specific departure */
 #define ENETC_PTCTSDR(n)       (0x1210 + 4 * (n))

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_qos.c b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
index 2e783ef73690f30ba0e5e8abed435ab963ef54a2..ee28cb62afe8d969eaf722a4ff76670700bfe87d 100644 (file)
--- a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
@@ -11,8 +11,7 @@
 
 static u16 enetc_get_max_gcl_len(struct enetc_hw *hw)
 {
-       return enetc_rd(hw, ENETC_QBV_PTGCAPR_OFFSET)
-               & ENETC_QBV_MAX_GCL_LEN_MASK;
+       return enetc_rd(hw, ENETC_PTGCAPR) & ENETC_PTGCAPR_MAX_GCL_LEN_MASK;
 }
 
 void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed)
@@ -65,9 +64,9 @@ static int enetc_setup_taprio(struct net_device *ndev,
                return -EINVAL;
        gcl_len = admin_conf->num_entries;
 
-       tge = enetc_rd(hw, ENETC_QBV_PTGCR_OFFSET);
+       tge = enetc_rd(hw, ENETC_PTGCR);
        if (!admin_conf->enable) {
-               enetc_wr(hw, ENETC_QBV_PTGCR_OFFSET, tge & ~ENETC_QBV_TGE);
+               enetc_wr(hw, ENETC_PTGCR, tge & ~ENETC_PTGCR_TGE);
 
                priv->active_offloads &= ~ENETC_F_QBV;
 
@@ -115,11 +114,11 @@ static int enetc_setup_taprio(struct net_device *ndev,
        cbd.cls = BDCR_CMD_PORT_GCL;
        cbd.status_flags = 0;
 
-       enetc_wr(hw, ENETC_QBV_PTGCR_OFFSET, tge | ENETC_QBV_TGE);
+       enetc_wr(hw, ENETC_PTGCR, tge | ENETC_PTGCR_TGE);
 
        err = enetc_send_cmd(priv->si, &cbd);
        if (err)
-               enetc_wr(hw, ENETC_QBV_PTGCR_OFFSET, tge & ~ENETC_QBV_TGE);
+               enetc_wr(hw, ENETC_PTGCR, tge & ~ENETC_PTGCR_TGE);
 
        enetc_cbd_free_data_mem(priv->si, data_size, tmp, &dma);
 
@@ -299,7 +298,7 @@ int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data)
                return -EINVAL;
 
        /* TSD and Qbv are mutually exclusive in hardware */
-       if (enetc_rd(hw, ENETC_QBV_PTGCR_OFFSET) & ENETC_QBV_TGE)
+       if (enetc_rd(hw, ENETC_PTGCR) & ENETC_PTGCR_TGE)
                return -EBUSY;
 
        priv->tx_ring[tc]->tsd_enable = qopt->enable;