radv: use 1ull for alignment computations

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21757>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 2e7e278..a918586 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1373,7 +1373,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
        *
        * "dcc_alignment * 4" was determined by trial and error.
        */
-      surf->meta_size = align64(surf->surf_size >> 8, (1 << surf->meta_alignment_log2) * 4);
+      surf->meta_size = align64(surf->surf_size >> 8, (1ull << surf->meta_alignment_log2) * 4);
    }
 
    /* Make sure HTILE covers the whole miptree, because the shader reads
@@ -2527,14 +2527,14 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
 
    if (surf->fmask_size) {
       assert(config->info.samples >= 2);
-      surf->fmask_offset = align64(surf->total_size, 1 << surf->fmask_alignment_log2);
+      surf->fmask_offset = align64(surf->total_size, 1ull << surf->fmask_alignment_log2);
       surf->total_size = surf->fmask_offset + surf->fmask_size;
       surf->alignment_log2 = MAX2(surf->alignment_log2, surf->fmask_alignment_log2);
    }
 
    /* Single-sample CMASK is in a separate buffer. */
    if (surf->cmask_size && config->info.samples >= 2) {
-      surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2);
+      surf->cmask_offset = align64(surf->total_size, 1ull << surf->cmask_alignment_log2);
       surf->total_size = surf->cmask_offset + surf->cmask_size;
       surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2);
    }
@@ -2552,11 +2552,11 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
           !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
           surf->u.gfx9.color.dcc.display_equation_valid) {
          /* Add space for the displayable DCC buffer. */
-         surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.color.display_dcc_alignment_log2);
+         surf->display_dcc_offset = align64(surf->total_size, 1ull << surf->u.gfx9.color.display_dcc_alignment_log2);
          surf->total_size = surf->display_dcc_offset + surf->u.gfx9.color.display_dcc_size;
       }
 
-      surf->meta_offset = align64(surf->total_size, 1 << surf->meta_alignment_log2);
+      surf->meta_offset = align64(surf->total_size, 1ull << surf->meta_alignment_log2);
       surf->total_size = surf->meta_offset + surf->meta_size;
       surf->alignment_log2 = MAX2(surf->alignment_log2, surf->meta_alignment_log2);
    }

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 014a337..1db6a9b 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1487,7 +1487,7 @@ radv_image_alloc_single_sample_cmask(const struct radv_device *device,
 
    assert(image->info.storage_samples == 1);
 
-   surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2);
+   surf->cmask_offset = align64(surf->total_size, 1ull << surf->cmask_alignment_log2);
    surf->total_size = surf->cmask_offset + surf->cmask_size;
    surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2);
 }
@@ -1753,7 +1753,7 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in
          stride = mod_info->pPlaneLayouts[plane].rowPitch / image->planes[plane].surface.bpe;
       } else {
          offset = image->disjoint ? 0 :
-            align64(image->size, 1 << image->planes[plane].surface.alignment_log2);
+            align64(image->size, 1ull << image->planes[plane].surface.alignment_log2);
          stride = 0; /* 0 means no override */
       }