arm64: dts: ti: k3-j721s2-main: Add dts nodes for EHRPWMs
authorSinthu Raja <sinthu.raja@ti.com>
Fri, 21 Jul 2023 08:21:50 +0000 (13:51 +0530)
committerNishanth Menon <nm@ti.com>
Wed, 2 Aug 2023 04:46:10 +0000 (23:46 -0500)
Add dts nodes for 6 EHRPWM instances on SoC. Disable EHRPWM nodes in the
dtsi files and only enable the ones that are actually pinned out on a
given board in the board dts file.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Link: https://lore.kernel.org/r/20230721082150.12599-1-sinthu.raja@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

index ed79ab3..2fb90b8 100644 (file)
                        mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
                                        <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
                };
+
+               ehrpwm_tbclk: clock-controller@140 {
+                       compatible = "ti,am654-ehrpwm-tbclk";
+                       reg = <0x140 0x18>;
+                       #clock-cells = <1>;
+               };
+       };
+
+       main_ehrpwm0: pwm@3000000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3000000 0x00 0x100>;
+               power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm1: pwm@3010000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3010000 0x00 0x100>;
+               power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm2: pwm@3020000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3020000 0x00 0x100>;
+               power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm3: pwm@3030000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3030000 0x00 0x100>;
+               power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm4: pwm@3040000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3040000 0x00 0x100>;
+               power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
+       };
+
+       main_ehrpwm5: pwm@3050000 {
+               compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x00 0x3050000 0x00 0x100>;
+               power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
+               clock-names = "tbclk", "fck";
+               status = "disabled";
        };
 
        gic500: interrupt-controller@1800000 {