/* Gate clocks */
mstp0_clks: clocks@ffc80030 {
compatible = "renesas,r8a7779-mstp-clocks",
- "renesas,cpg-mstp-clocks";
+ "renesas,cpg-mstp-clocks";
reg = <0xffc80030 4>;
clocks = <&cpg_clocks R8A7779_CLK_S>,
- <&cpg_clocks R8A7779_CLK_P>,
+ <&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_S>,
};
mstp1_clks: clocks@ffc80034 {
compatible = "renesas,r8a7779-mstp-clocks",
- "renesas,cpg-mstp-clocks";
+ "renesas,cpg-mstp-clocks";
reg = <0xffc80034 4>, <0xffc80044 4>;
clocks = <&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
};
mstp3_clks: clocks@ffc8003c {
compatible = "renesas,r8a7779-mstp-clocks",
- "renesas,cpg-mstp-clocks";
+ "renesas,cpg-mstp-clocks";
reg = <0xffc8003c 4>;
clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
<&s4_clk>, <&s4_clk>;