-/**
- ******************************************************************************
- * @file pinctrl-starfive-jh7110.c
- * @author StarFive Technology
- * @version V1.0
- * @date 11/30/2021
- * @brief
- ******************************************************************************
- * @copy
- *
- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
- */
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
+#include <linux/module.h>
#include "../core.h"
#include "../pinconf.h"
#include "pinctrl-starfive.h"
/***************sys_iomux***************/
-#define SYS_GPO_DOEN_CFG_BASE_REG 0x0
-#define SYS_GPO_DOEN_CFG_END_REG 0x3c
+#define SYS_GPO_DOEN_CFG_BASE_REG 0x0
+#define SYS_GPO_DOEN_CFG_END_REG 0x3c
-#define SYS_GPO_DOUT_CFG_BASE_REG 0x40
-#define SYS_GPO_DOUT_CFG_END_REG 0x7c
+#define SYS_GPO_DOUT_CFG_BASE_REG 0x40
+#define SYS_GPO_DOUT_CFG_END_REG 0x7c
#define SYS_GPI_DIN_CFG_BASE_REG 0x80
#define SYS_GPI_DIN_CFG_END_REG 0xd8
/*sys_iomux PIN 0-74 ioconfig reg*/
-#define SYS_GPO_PDA_0_74_CFG_BASE_REG 0x120
-#define SYS_GPO_PDA_0_74_CFG_END_REG 0x248
+#define SYS_GPO_PDA_0_74_CFG_BASE_REG 0x120
+#define SYS_GPO_PDA_0_74_CFG_END_REG 0x248
/*sys_iomux PIN 75-88 gamc1 no ioconfig reg*/
/*sys_iomux PIN 89-94 ioconfig reg*/
-#define SYS_GPO_PDA_89_94_CFG_BASE_REG 0x284
+#define SYS_GPO_PDA_89_94_CFG_BASE_REG 0x284
#define SYS_GPO_PDA_89_94_CFG_END_REG 0x298
//sys_iomux GPIO CTRL
#define GPIO_INPUT_ENABLE_X_REG 0x120
-#define MAX_GPIO 64
+#define MAX_GPIO 64
/***************sys_iomux***************/
/***************aon_iomux***************/
-#define AON_GPO_DOEN_CFG_BASE_REG 0x0
-#define AON_GPO_DOUT_CFG_BASE_REG 0x4
+#define AON_GPO_DOEN_CFG_BASE_REG 0x0
+#define AON_GPO_DOUT_CFG_BASE_REG 0x4
#define AON_GPI_DIN_CFG_BASE_REG 0x8
//aon_iomux GPIO CTRL
#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_9_ADDR (0x24U)
#define AON_GPIORIS_0_REG_SHIFT 0x0U
#define AON_GPIORIS_0_REG_MASK 0xFU
-#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_10_ADDR (0x28U)
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_10_ADDR (0x28U)
#define AON_GPIOMIS_0_REG_SHIFT 0x0U
#define AON_GPIOMIS_0_REG_MASK 0xFU
-#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_11_ADDR (0x2cU)
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_11_ADDR (0x2cU)
#define AON_GPIO_IN_SYNC2_0_REG_SHIFT 0x0U
#define AON_GPIO_IN_SYNC2_0_REG_MASK 0xFU
#define GPO_PDA_CFG_OFFSET 0x4U
/*one dword include 4 gpios*/
-#define GPIO_NUM_SHIFT 2
+#define GPIO_NUM_SHIFT 2
/*8 bits for each gpio*/
#define GPIO_BYTE_SHIFT 3
/*gpio index in dword */
-#define GPIO_INDEX_MASK 0x3
-#define GPIO_VAL_MASK 0x7f
+#define GPIO_INDEX_MASK 0x3
+#define GPIO_VAL_MASK 0x7f
enum starfive_jh7110_sys_pads {
PAD_GPIO0 = 0,
/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc starfive_jh7110_sys_pinctrl_pads[]= {
+static const struct pinctrl_pin_desc starfive_jh7110_sys_pinctrl_pads[] = {
STARFIVE_PINCTRL_PIN(PAD_GPIO0),
STARFIVE_PINCTRL_PIN(PAD_GPIO1),
STARFIVE_PINCTRL_PIN(PAD_GPIO2),
PAD_GMAC0_TXC = 19,
};
-static const struct pinctrl_pin_desc starfive_jh7110_aon_pinctrl_pads[]= {
+static const struct pinctrl_pin_desc starfive_jh7110_aon_pinctrl_pads[] = {
STARFIVE_PINCTRL_PIN(PAD_TESTEN),
STARFIVE_PINCTRL_PIN(PAD_RGPIO0),
STARFIVE_PINCTRL_PIN(PAD_RGPIO1),
STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXC),
};
-static void pinctrl_write_reg(volatile void __iomem *addr, u32 mask, u32 val)
+static void pinctrl_write_reg(void __iomem *addr, u32 mask, u32 val)
{
u32 value;
- value= readl_relaxed(addr);
+ value = readl_relaxed(addr);
value &= ~mask;
value |= (val & mask);
- writel_relaxed(value,addr);
+ writel_relaxed(value, addr);
}
-uint32_t pinctrl_get_reg(volatile void __iomem *addr,u32 shift,u32 mask)
+uint32_t pinctrl_get_reg(void __iomem *addr, u32 shift, u32 mask)
{
u32 tmp;
- tmp= readl_relaxed(addr);
- tmp= (tmp & mask) >> shift;
+
+ tmp = readl_relaxed(addr);
+ tmp = (tmp & mask) >> shift;
return tmp;
}
-void pinctrl_set_reg(volatile void __iomem *addr,u32 data,u32 shift,u32 mask)
+void pinctrl_set_reg(void __iomem *addr, u32 data, u32 shift, u32 mask)
{
u32 tmp;
- tmp= readl_relaxed(addr);
+ tmp = readl_relaxed(addr);
tmp &= ~mask;
tmp |= (data<<shift) & mask;
- writel_relaxed(tmp,addr);
+ writel_relaxed(tmp, addr);
}
static int starfive_jh7110_sys_direction_input(struct gpio_chip *gc,
- unsigned offset)
+ unsigned int offset)
{
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
unsigned long flags;
if (offset >= gc->ngpio)
return -EINVAL;
-
+
raw_spin_lock_irqsave(&chip->lock, flags);
- v= readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+ v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
v &= ~(0x3f << ((offset & 0x3) * 8));
v |= 1 << ((offset & 0x3) * 8);
writel_relaxed(v, chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
return 0;
}
-static int starfive_jh7110_sys_direction_output(struct gpio_chip *gc,
- unsigned offset,
+static int starfive_jh7110_sys_direction_output(struct gpio_chip *gc,
+ unsigned int offset,
int value)
{
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
if (offset >= gc->ngpio)
return -EINVAL;
-
+
raw_spin_lock_irqsave(&chip->lock, flags);
- v= readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+ v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
v &= ~(0x3f << ((offset & 0x3) * 8));
writel_relaxed(v, chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
- v= readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
+ v = readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
v &= ~(0x7f << ((offset & 0x3) * 8));
v |= value << ((offset & 0x3) * 8);
writel_relaxed(v, chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
}
static int starfive_jh7110_sys_get_direction(struct gpio_chip *gc,
- unsigned offset)
+ unsigned int offset)
{
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
unsigned int v;
if (offset >= gc->ngpio)
return -EINVAL;
- v= readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+ v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
return !!(v & (0x3f << ((offset & 0x3) * 8)));
}
static int starfive_jh7110_sys_get_value(struct gpio_chip *gc,
- unsigned offset)
+ unsigned int offset)
{
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
int value;
+ int tmp;
if (offset >= gc->ngpio)
return -EINVAL;
- if(offset < 32){
- value= readl_relaxed(chip->padctl_base + GPIO_DIN_LOW);
- return (value >> offset) & 0x1;
+ if (offset < 32) {
+ value = readl_relaxed(chip->padctl_base + GPIO_DIN_LOW);
+ tmp = 0;
} else {
- value= readl_relaxed(chip->padctl_base + GPIO_DIN_HIGH);
- return (value >> (offset - 32)) & 0x1;
+ value = readl_relaxed(chip->padctl_base + GPIO_DIN_HIGH);
+ tmp = 32;
}
+ return (value >> (offset - tmp)) & 0x1;
}
-static void starfive_jh7110_sys_set_value(struct gpio_chip *gc,
- unsigned offset,
+static void starfive_jh7110_sys_set_value(struct gpio_chip *gc,
+ unsigned int offset,
int value)
{
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
return;
raw_spin_lock_irqsave(&chip->lock, flags);
- v= readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
+ v = readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
v &= ~(0x7f << ((offset & 0x3) * 8));
v |= value << ((offset & 0x3) * 8);
writel_relaxed(v, chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
int old_value, new_value;
int reg_offset, index;
- if(offset < 32) {
- reg_offset= 0;
- index= offset;
+ if (offset < 32) {
+ reg_offset = 0;
+ index = offset;
} else {
- reg_offset= 4;
- index= offset - 32;
+ reg_offset = 4;
+ index = offset - 32;
}
raw_spin_lock_irqsave(&chip->lock, flags);
- old_value= readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
- new_value= old_value | ( 1 << index);
+ old_value = readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ new_value = old_value | (1 << index);
writel_relaxed(new_value, chip->padctl_base + GPIO_IE_LOW + reg_offset);
raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int starfive_jh7110_sys_irq_set_type(struct irq_data *d,
- unsigned trigger)
+ unsigned int trigger)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
- int offset= irqd_to_hwirq(d);
+ int offset = irqd_to_hwirq(d);
unsigned int reg_is, reg_ibe, reg_iev;
int reg_offset, index;
if (offset < 0 || offset >= gc->ngpio)
return -EINVAL;
- if(offset < 32) {
- reg_offset= 0;
- index= offset;
+ if (offset < 32) {
+ reg_offset = 0;
+ index = offset;
} else {
- reg_offset= 4;
- index= offset - 32;
+ reg_offset = 4;
+ index = offset - 32;
}
- switch(trigger) {
+ switch (trigger) {
case IRQ_TYPE_LEVEL_HIGH:
- reg_is= readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
- reg_ibe= readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
- reg_iev= readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
- reg_is &= (~(0x1<< index));
- reg_ibe &= (~(0x1<< index));
- reg_iev |= (~(0x1<< index));
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is &= (~(0x1 << index));
+ reg_ibe &= (~(0x1 << index));
+ reg_iev |= (~(0x1 << index));
writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
break;
case IRQ_TYPE_LEVEL_LOW:
- reg_is= readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
- reg_ibe= readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
- reg_iev= readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
- reg_is &= (~(0x1<< index));
- reg_ibe &= (~(0x1<< index));
- reg_iev &= (0x1<< index);
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is &= (~(0x1 << index));
+ reg_ibe &= (~(0x1 << index));
+ reg_iev &= (0x1 << index);
writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
break;
case IRQ_TYPE_EDGE_BOTH:
- reg_is= readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
- reg_ibe= readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
- reg_iev= readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
- reg_is |= (0x1<< index);
- reg_ibe |= (0x1<< index);
- reg_iev |= (~(0x1<< index));
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is |= (0x1 << index);
+ reg_ibe |= (0x1 << index);
+ reg_iev |= (~(0x1 << index));
writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
break;
case IRQ_TYPE_EDGE_RISING:
- reg_is= readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
- reg_ibe= readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
- reg_iev= readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
- reg_is |= (0x1<< index);
- reg_ibe &= (~(0x1<< index));
- reg_iev |= (0x1<< index);
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is |= (0x1 << index);
+ reg_ibe &= (~(0x1 << index));
+ reg_iev |= (0x1 << index);
writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
break;
case IRQ_TYPE_EDGE_FALLING:
- reg_is= readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
- reg_ibe= readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
- reg_iev= readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
- reg_is |= (0x1<< index);
- reg_ibe &= (~(0x1<< index));
- reg_iev &= (~(0x1<< index));
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is |= (0x1 << index);
+ reg_ibe &= (~(0x1 << index));
+ reg_iev &= (~(0x1 << index));
writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
break;
}
- chip->trigger[offset]= trigger;
+ chip->trigger[offset] = trigger;
starfive_jh7110_sys_set_ie(chip, offset);
return 0;
}
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
unsigned int value;
- int offset= irqd_to_hwirq(d);
+ int offset = irqd_to_hwirq(d);
int reg_offset, index;
if (offset < 0 || offset >= gc->ngpio)
return;
- if(offset < 32) {
- reg_offset= 0;
- index= offset;
+ if (offset < 32) {
+ reg_offset = 0;
+ index = offset;
} else {
- reg_offset= 4;
- index= offset - 32;
+ reg_offset = 4;
+ index = offset - 32;
}
- value= readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ value = readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
value &= ~(0x1 << index);
- writel_relaxed(value,chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ writel_relaxed(value, chip->padctl_base + GPIO_IE_LOW + reg_offset);
}
static void starfive_jh7110_sys_irq_unmask(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct starfive_pinctrl *chip = gpiochip_get_data(gc);
unsigned int value;
- int offset= irqd_to_hwirq(d);
+ int offset = irqd_to_hwirq(d);
int reg_offset, index;
if (offset < 0 || offset >= gc->ngpio)
return;
- if(offset < 32) {
- reg_offset= 0;
- index= offset;
+ if (offset < 32) {
+ reg_offset = 0;
+ index = offset;
} else {
- reg_offset= 4;
- index= offset - 32;
+ reg_offset = 4;
+ index = offset - 32;
}
- value= readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ value = readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
value |= (0x1 << index);
- writel_relaxed(value,chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ writel_relaxed(value, chip->padctl_base + GPIO_IE_LOW + reg_offset);
}
static void starfive_jh7110_sys_irq_enable(struct irq_data *d)
starfive_jh7110_sys_set_ie(chip, offset);
}
-static struct irq_chip starfive_jh7110_sys_irqchip= {
+static struct irq_chip starfive_jh7110_sys_irqchip = {
.name = "starfive_jh7110_sys-gpio",
.irq_set_type = starfive_jh7110_sys_irq_set_type,
.irq_mask = starfive_jh7110_sys_irq_mask,
unsigned long flags;
struct starfive_pinctrl *chip = gc;
- for (offset= 0; offset < 64; offset++) {
- if(offset < 32) {
- reg_offset= 0;
- index= offset;
+ for (offset = 0; offset < 64; offset++) {
+ if (offset < 32) {
+ reg_offset = 0;
+ index = offset;
} else {
- reg_offset= 4;
- index= offset - 32;
+ reg_offset = 4;
+ index = offset - 32;
}
raw_spin_lock_irqsave(&chip->lock, flags);
- value= readl_relaxed(chip->padctl_base + GPIO_MIS_LOW + reg_offset);
- if(value & BIT(index))
+ value = readl_relaxed(chip->padctl_base + GPIO_MIS_LOW + reg_offset);
+ if (value & BIT(index))
writel_relaxed(BIT(index), chip->padctl_base + GPIO_IC_LOW +
reg_offset);
platform_set_drvdata(pdev, pctl);
ret = gpiochip_add_data(&pctl->gc, pctl);
- if (ret){
- dev_err(dev, "gpiochip_add_data ret=%d!\n", ret);
- return ret;
- }
-
-#if 0
- /* Disable all GPIO interrupts before enabling parent interrupts */
- iowrite32(0, pctl->padctl_base + GPIO_IE_HIGH);
- iowrite32(0, pctl->padctl_base + GPIO_IE_LOW);
- pctl->enabled = 0;
-
- ret = gpiochip_irqchip_add(&pctl->gc, &starfive_jh7110_sys_irqchip, 0,
- handle_simple_irq, IRQ_TYPE_NONE);
if (ret) {
- dev_err(dev, "could not add irqchip\n");
- gpiochip_remove(&pctl->gc);
+ dev_err(dev, "gpiochip_add_data ret=%d!\n", ret);
return ret;
}
-#endif
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
writel_relaxed(1, pctl->padctl_base + GPIO_EN);
- for(loop = 0; loop < MAX_GPIO; loop++) {
+ for (loop = 0; loop < MAX_GPIO; loop++) {
unsigned int v;
+
v = readl_relaxed(pctl->padctl_base + GPIO_INPUT_ENABLE_X_REG + (loop << 2));
v |= 0x1;
writel_relaxed(v, pctl->padctl_base + GPIO_INPUT_ENABLE_X_REG + (loop << 2));
-static int starfive_jh7110_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id,
+static int starfive_jh7110_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
unsigned long *config)
{
struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct starfive_pinctrl_soc_info *info = pctl->info;
const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
u32 value;
-
+
if (pin_reg->io_conf_reg == -1) {
dev_err(pctl->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
}
-
+
value = readl_relaxed(pctl->padctl_base + pin_reg->io_conf_reg);
- *config = value & 0xff;
+ *config = value & 0xff;
return 0;
}
-
+
static int starfive_jh7110_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
+ unsigned int pin_id, unsigned long *configs,
+ unsigned int num_configs)
{
struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct starfive_pinctrl_soc_info *info = pctl->info;
info->pins[pin_id].name);
return -EINVAL;
}
-
+
raw_spin_lock_irqsave(&pctl->lock, flags);
- for (i= 0; i < num_configs; i++) {
+ for (i = 0; i < num_configs; i++) {
value = readl_relaxed(pctl->padctl_base + pin_reg->io_conf_reg);
value = value|(configs[i] & 0xFF);
writel_relaxed(value, pctl->padctl_base + pin_reg->io_conf_reg);
- }
+ }
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
const struct starfive_pinctrl_soc_info *info = pctl->info;
struct starfive_pin_config *pin_config = &pin->pin_config;
const struct starfive_pin_reg *pin_reg;
- unsigned int gpio,pin_id;
+ unsigned int gpio, pin_id;
int i;
unsigned long flags;
- int n,shift;
+ int n, shift;
gpio = pin->pin_config.gpio_num;
pin_id = pin->pin;
pin_reg = &pctl->pin_regs[pin_id];
-
+
raw_spin_lock_irqsave(&pctl->lock, flags);
- if(pin_reg->func_sel_reg != -1){
+ if (pin_reg->func_sel_reg != -1) {
pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
pin_config->pinmux_func, pin_reg->func_sel_shift,
pin_reg->func_sel_mask);
}
-
+
shift = (gpio & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT;
- if(pin_reg->gpo_dout_reg != -1){
- pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
+ if (pin_reg->gpo_dout_reg != -1) {
+ pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
0x7F<<shift, pin_config->gpio_dout<<shift);
}
- if(pin_reg->gpo_doen_reg != -1){
- pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
+ if (pin_reg->gpo_doen_reg != -1) {
+ pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
0x3F<<shift, pin_config->gpio_doen<<shift);
}
- for(i = 0; i < pin_config->gpio_din_num; i++){
+ for (i = 0; i < pin_config->gpio_din_num; i++) {
n = pin_config->gpio_din_reg[i] >> 2;
shift = (pin_config->gpio_din_reg[i] & 3) << 3;
pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
0x3F<<shift, (gpio+2)<<shift);
}
- if(pin_reg->syscon_reg != -1){
- pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
+ if (pin_reg->syscon_reg != -1) {
+ pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
pin_config->syscon, PADCFG_PAD_GMAC_SYSCON_SHIFT,
PADCFG_PAD_GMAC_SYSCON_MASK);
}
- if(pin_reg->pad_sel_reg != -1){
+ if (pin_reg->pad_sel_reg != -1) {
pinctrl_set_reg(pctl->padctl_base + pin_reg->pad_sel_reg,
pin_config->padmux_func, pin_reg->pad_sel_shift,
pin_reg->pad_sel_mask);
}
raw_spin_unlock_irqrestore(&pctl->lock, flags);
-
+
return 0;
}
u32 value;
int i;
int n;
-
+
pin_size = 4;
*pins_id = be32_to_cpu(*list);
pin_reg = &pctl->pin_regs[*pins_id];
pin_data->pin = *pins_id;
- if(pin_data->pin > PAD_QSPI_DATA3){
- dev_err(pctl->dev,"err pin num\n");
+ if (pin_data->pin > PAD_QSPI_DATA3) {
+ dev_err(pctl->dev, "err pin num\n");
return;
}
- if(pin_data->pin < PAD_GMAC1_MDC){
- pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
+ if (pin_data->pin < PAD_GMAC1_MDC) {
+ pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
+ SYS_GPO_PDA_0_74_CFG_BASE_REG;
- }
- else if(pin_data->pin > PAD_GMAC1_TXC){
- pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
- + SYS_GPO_PDA_89_94_CFG_BASE_REG;
+ } else if (pin_data->pin > PAD_GMAC1_TXC) {
+ pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
+ + SYS_GPO_PDA_89_94_CFG_BASE_REG;
}
- if (!of_property_read_u32(np, "sf,pin-ioconfig", &value)) {
+ if (!of_property_read_u32(np, "sf,pin-ioconfig", &value))
pin_data->pin_config.io_config = value;
- }
list = of_get_property(np, "sf,pinmux", &size);
if (list) {
if (list) {
pin_reg->syscon_reg = be32_to_cpu(*list++);
pin_data->pin_config.syscon = be32_to_cpu(*list++);
- }
+ }
- if(pin_data->pin < PAD_SD0_CLK){
+ if (pin_data->pin < PAD_SD0_CLK) {
pin_data->pin_config.gpio_num = pin_data->pin;
- n= pin_data->pin_config.gpio_num >> GPIO_NUM_SHIFT;
-
+ n = pin_data->pin_config.gpio_num >> GPIO_NUM_SHIFT;
+
if (!of_property_read_u32(np, "sf,pin-gpio-dout", &value)) {
pin_data->pin_config.gpio_dout = value;
pin_reg->gpo_dout_reg = info->dout_reg_base + n * 4;
}
-
+
if (!of_property_read_u32(np, "sf,pin-gpio-doen", &value)) {
pin_data->pin_config.gpio_doen = value;
pin_reg->gpo_doen_reg = info->doen_reg_base + n * 4;
list_din = of_get_property(np, "sf,pin-gpio-din", &size_din);
if (list_din) {
if (!size_din || size_din % pin_size) {
- dev_err(pctl->dev,
+ dev_err(pctl->dev,
"Invalid sf,pin-gpio-din property in node\n");
return;
}
-
+
pin_data->pin_config.gpio_din_num = size_din / pin_size;
pin_data->pin_config.gpio_din_reg = devm_kcalloc(pctl->dev,
pin_data->pin_config.gpio_din_num,
sizeof(s32),
GFP_KERNEL);
-
- for(i = 0; i < pin_data->pin_config.gpio_din_num; i++){
+
+ for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
value = be32_to_cpu(*list_din++);
pin_data->pin_config.gpio_din_reg[i] = value;
}
}
}
- return;
}
static const struct starfive_pinctrl_soc_info starfive_jh7110_sys_pinctrl_info = {
const struct starfive_pinctrl_soc_info *info = pctl->info;
struct starfive_pin_config *pin_config = &pin->pin_config;
const struct starfive_pin_reg *pin_reg;
- unsigned int gpio,pin_id;
+ unsigned int gpio, pin_id;
int i;
unsigned long flags;
- int n,shift;
-
+ int n, shift;
+
gpio = pin->pin_config.gpio_num;
pin_id = pin->pin;
pin_reg = &pctl->pin_regs[pin_id];
-
+
raw_spin_lock_irqsave(&pctl->lock, flags);
- if(pin_reg->func_sel_reg != -1){
+ if (pin_reg->func_sel_reg != -1) {
pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
pin_config->pinmux_func,
pin_reg->func_sel_shift,
pin_reg->func_sel_mask);
}
-
+
shift = (gpio & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT;
- if(pin_reg->gpo_dout_reg != -1){
- pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
+ if (pin_reg->gpo_dout_reg != -1) {
+ pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
0xF << shift,
pin_config->gpio_dout<<shift);
-
}
- if(pin_reg->gpo_doen_reg != -1){
+ if (pin_reg->gpo_doen_reg != -1) {
pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
0x7 << shift,
pin_config->gpio_doen << shift);
-
}
- for(i = 0; i < pin_config->gpio_din_num; i++){
+ for (i = 0; i < pin_config->gpio_din_num; i++) {
n = pin_config->gpio_din_reg[i] >> 2;
shift = (pin_config->gpio_din_reg[i] & 3) << 3;
- pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
+ pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
0x7 << shift,
(gpio+2) << shift);
}
- if(pin_reg->syscon_reg != -1){
- pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
+ if (pin_reg->syscon_reg != -1) {
+ pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
pin_config->syscon,
PADCFG_PAD_GMAC_SYSCON_SHIFT,
PADCFG_PAD_GMAC_SYSCON_MASK);
}
-
+
raw_spin_unlock_irqrestore(&pctl->lock, flags);
-
+
return 0;
}
int pin_size;
u32 value;
int i;
-
+
pin_size = 4;
*pins_id = be32_to_cpu(*list);
pin_reg = &pctl->pin_regs[*pins_id];
pin_data->pin = *pins_id;
-
- if(pin_data->pin > PAD_GMAC0_TXC){
- dev_err(pctl->dev,"err pin num\n");
+
+ if (pin_data->pin > PAD_GMAC0_TXC) {
+ dev_err(pctl->dev, "err pin num\n");
return;
}
-
- if(pin_data->pin < PAD_GMAC0_MDC){
- pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET) +
+
+ if (pin_data->pin < PAD_GMAC0_MDC) {
+ pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET) +
AON_GPO_PDA_0_5_CFG_BASE_REG;
}
- if (!of_property_read_u32(np, "sf,pin-ioconfig", &value)) {
+ if (!of_property_read_u32(np, "sf,pin-ioconfig", &value))
pin_data->pin_config.io_config = value;
- }
list = of_get_property(np, "sf,pinmux", &size);
if (list) {
pin_reg->func_sel_mask = be32_to_cpu(*list++);
pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
}
-
+
list = of_get_property(np, "sf,pin-syscon", &size);
if (list) {
pin_reg->syscon_reg = be32_to_cpu(*list++);
pin_data->pin_config.syscon = be32_to_cpu(*list++);
}
- if((pin_data->pin >= PAD_RGPIO0) && (pin_data->pin <= PAD_RGPIO3)){
+ if ((pin_data->pin >= PAD_RGPIO0) && (pin_data->pin <= PAD_RGPIO3)) {
pin_data->pin_config.gpio_num = pin_data->pin;
pin_reg->gpo_dout_reg = info->dout_reg_base;
pin_reg->gpo_doen_reg = info->doen_reg_base;
- if (!of_property_read_u32(np, "sf,pin-gpio-dout", &value)) {
+ if (!of_property_read_u32(np, "sf,pin-gpio-dout", &value))
pin_data->pin_config.gpio_dout = value;
- }
-
- if (!of_property_read_u32(np, "sf,pin-gpio-doen", &value)) {
+
+ if (!of_property_read_u32(np, "sf,pin-gpio-doen", &value))
pin_data->pin_config.gpio_doen = value;
- }
-
+
list_din = of_get_property(np, "sf,pin-gpio-din", &size_din);
if (list_din) {
if (!size_din || size_din % pin_size) {
- dev_err(pctl->dev,
+ dev_err(pctl->dev,
"Invalid sf,pin-gpio-din property in node\n");
return;
}
pin_data->pin_config.gpio_din_num,
sizeof(s32),
GFP_KERNEL);
- for(i = 0; i < pin_data->pin_config.gpio_din_num; i++){
+ for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
value = be32_to_cpu(*list_din++);
pin_data->pin_config.gpio_din_reg[i] = value;
}
}
}
- return;
}
static const struct starfive_pinctrl_soc_info starfive_jh7110_aon_pinctrl_info = {
.compatible = "starfive_jh7110-sys-pinctrl",
.data = &starfive_jh7110_sys_pinctrl_info,
},
- {
- .compatible = "starfive_jh7110-aon-pinctrl",
- .data = &starfive_jh7110_aon_pinctrl_info,
+ {
+ .compatible = "starfive_jh7110-aon-pinctrl",
+ .data = &starfive_jh7110_aon_pinctrl_info,
},
{ /* sentinel */ }
};
pinctrl_info = of_device_get_match_data(&pdev->dev);
if (!pinctrl_info)
return -ENODEV;
-
+
return starfive_pinctrl_probe(pdev, pinctrl_info);
}
return platform_driver_register(&starfive_jh7110_pinctrl_driver);
}
arch_initcall(starfive_jh7110_pinctrl_init);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC");
+MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
-/**
- ******************************************************************************
- * @file pinctrl-starfive.c
- * @author StarFive Technology
- * @version V1.0
- * @date 11/30/2021
- * @brief
- ******************************************************************************
- * @copy
- *
- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
- */
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ */
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
{
const struct group_desc *grp = NULL;
int i;
-
+
for (i = 0; i < pctldev->num_groups; i++) {
grp = pinctrl_generic_get_group(pctldev, i);
if (grp && !strcmp(grp->name, name))
}
static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned offset)
+ unsigned int offset)
{
seq_printf(s, "%s", dev_name(pctldev->dev));
}
static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
- struct pinctrl_map **map, unsigned *num_maps)
+ struct pinctrl_map **map, unsigned int *num_maps)
{
struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct group_desc *grp;
struct device_node *parent;
struct starfive_pin *pin;
int map_num = 1;
- int i, j;
+ int i, j;
grp = starfive_pinctrl_find_group_by_name(pctldev, np->name);
if (!grp) {
dev_err(pctl->dev, "unable to find group for node %pOFn\n", np);
return -EINVAL;
}
-
+
map_num = grp->num_pins + 1;
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
GFP_KERNEL);
}
static void starfive_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned num_maps)
+ struct pinctrl_map *map, unsigned int num_maps)
{
kfree(map);
}
};
-static int starfive_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
+static int starfive_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector,
+ unsigned int group)
{
struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct starfive_pinctrl_soc_info *info = pctl->info;
for (i = 0; i < npins; i++) {
pin = &((struct starfive_pin *)(grp->data))[i];
- if(info->starfive_pmx_set_one_pin_mux){
+ if (info->starfive_pmx_set_one_pin_mux) {
err = info->starfive_pmx_set_one_pin_mux(pctl, pin);
if (err)
return err;
return 0;
}
-struct pinmux_ops starfive_pmx_ops = {
+const struct pinmux_ops starfive_pmx_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
+ unsigned int pin_id, unsigned long *config)
{
struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct starfive_pinctrl_soc_info *info = pctl->info;
-
- if(info->starfive_pinconf_get)
+
+ if (info->starfive_pinconf_get)
return info->starfive_pinconf_get(pctldev, pin_id, config);
-
+
return 0;
}
static int starfive_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
+ unsigned int pin_id, unsigned long *configs,
+ unsigned int num_configs)
{
struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct starfive_pinctrl_soc_info *info = pctl->info;
-
- if(info->starfive_pinconf_set)
+
+ if (info->starfive_pinconf_set)
return info->starfive_pinconf_set(pctldev, pin_id,
configs, num_configs);
return 0;
}
static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned pin_id)
+ struct seq_file *s, unsigned int pin_id)
{
struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct starfive_pin_reg *pin_reg;
seq_puts(s, "N/A");
return;
}
-
+
ret = starfive_pinconf_get(pctldev, pin_id, &config);
if (ret)
return;
}
static void starfive_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned group)
+ struct seq_file *s, unsigned int group)
{
struct group_desc *grp;
unsigned long config;
int offset = 0;
const __be32 *list;
int j, child_num_pins;
-
+
pin_size = STARFIVE_PINS_SIZE;
/* Initialise group */
grp->name = np->name;
-
+
for_each_child_of_node(np, child) {
list = of_get_property(child, "sf,pins", &psize);
if (!list) {
"Invalid sf,pins or pins property in node %pOF\n", np);
return -EINVAL;
}
-
+
grp->num_pins = size / pin_size;
grp->data = devm_kcalloc(pctl->dev,
grp->num_pins, sizeof(struct starfive_pin),
grp->num_pins, sizeof(int),
GFP_KERNEL);
if (!grp->pins || !grp->data)
- return -ENOMEM;
-
+ return -ENOMEM;
+
for_each_child_of_node(np, child) {
list = of_get_property(child, "sf,pins", &psize);
if (!list) {
"no sf,pins and pins property in node %pOF\n", np);
return -EINVAL;
}
-
+
child_num_pins = psize / pin_size;
for (j = 0; j < child_num_pins; j++) {
pin_data = &((struct starfive_pin *)(grp->data))[j + offset];
pins_id = &(grp->pins)[j + offset];
-
- if (!info->starfive_pinctrl_parse_pin){
+
+ if (!info->starfive_pinctrl_parse_pin) {
dev_err(pctl->dev, "pinmux ops lacks necessary functions\n");
return -EINVAL;
}
-
- info->starfive_pinctrl_parse_pin(pctl, pins_id,pin_data, list, child);
+
+ info->starfive_pinctrl_parse_pin(pctl, pins_id, pin_data, list, child);
list++;
}
offset += j;
}
-
+
return 0;
}
struct device_node *child;
struct function_desc *func;
struct group_desc *grp;
- u32 i = 0;
+ u32 i = 0;
int ret;
func = pinmux_generic_get_function(pctldev, index);
sizeof(char *), GFP_KERNEL);
if (!func->group_names)
return -ENOMEM;
-
+
for_each_child_of_node(np, child) {
func->group_names[i] = child->name;
grp = devm_kzalloc(pctl->dev, sizeof(struct group_desc),
of_node_put(child);
return -ENOMEM;
}
-
+
mutex_lock(&pctl->mutex);
radix_tree_insert(&pctldev->pin_group_tree,
pctl->group_index++, grp);
mutex_unlock(&pctl->mutex);
ret = starfive_pinctrl_parse_groups(child, grp, pctl, i++);
- if (ret < 0){
+ if (ret < 0) {
dev_err(pctl->dev, "parse groups failed\n");
return ret;
}
radix_tree_insert(&pctldev->pin_function_tree, i, function);
mutex_unlock(&pctl->mutex);
}
-
+
pctldev->num_functions = nfuncs;
pctl->group_index = 0;
pctldev->num_groups = of_get_child_count(np);
starfive_pinctrl_parse_functions(np, pctl, 0);
- return 0;
+ return 0;
}
int starfive_pinctrl_probe(struct platform_device *pdev,
pctl->pin_regs[i].syscon_reg = -1;
pctl->pin_regs[i].pad_sel_reg = -1;
}
-
+
pctl->padctl_base = devm_platform_ioremap_resource_byname(pdev, "control");
if (IS_ERR(pctl->padctl_base))
return PTR_ERR(pctl->padctl_base);
if (IS_ERR(pctl->gpio_base))
return PTR_ERR(pctl->gpio_base);
}
-
+
if (info->starfive_iopad_sel_func) {
- ret = info->starfive_iopad_sel_func(pdev,pctl,value);
- if (ret)
+ ret = info->starfive_iopad_sel_func(pdev, pctl, value);
+ if (ret)
return ret;
}
GFP_KERNEL);
if (!starfive_pinctrl_desc)
return -ENOMEM;
-
+
raw_spin_lock_init(&pctl->lock);
starfive_pinctrl_desc->name = dev_name(&pdev->dev);
starfive_pinctrl_desc, pctl,
&pctl->pctl_dev);
if (ret) {
- dev_err(&pdev->dev,
+ dev_err(&pdev->dev,
"could not register starfive pinctrl driver\n");
return ret;
}
ret = starfive_pinctrl_probe_dt(pdev, pctl);
if (ret) {
- dev_err(&pdev->dev,
+ dev_err(&pdev->dev,
"fail to probe dt properties\n");
return ret;
}
-
+
ret = pinctrl_enable(pctl->pctl_dev);
if (ret) {
- dev_err(&pdev->dev,
+ dev_err(&pdev->dev,
"pin controller failed to start\n");
return ret;
}
- if(info->starfive_gpio_register){
- ret = info->starfive_gpio_register(pdev,pctl);
+ if (info->starfive_gpio_register) {
+ ret = info->starfive_gpio_register(pdev, pctl);
if (ret) {
dev_err(&pdev->dev,
"starfive_gpio_register failed to register\n");
starfive_pinctrl_resume)
};
EXPORT_SYMBOL_GPL(starfive_pinctrl_pm_ops);
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC");
MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
MODULE_LICENSE("GPL v2");
projects / platform / kernel / linux-starfive.git / commitdiff