[POWERPC] 4xx: Add L2 cache node to AMCC Taishan dts file

This patch adds the L2 cache node to the Taishan 440GX dts file.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 3d0334cec55c5441efeef992dcb7865d6587a52d..96d033d6c05eca082a2ecfc398d5820b01ff2612 100644 (file)
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -104,6 +104,16 @@
                // FIXME: anything else?
        };
 
+       L2C0: l2c {
+               compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+               dcr-reg = <20 8                 /* Internal SRAM DCR's */
+                          30 8>;               /* L2 cache DCR's */
+               cache-line-size = <20>;         /* 32 bytes */
+               cache-size = <40000>;           /* L2, 256K */
+               interrupt-parent = <&UIC2>;
+               interrupts = <17 1>;
+       };
+
        plb {
                compatible = "ibm,plb-440gx", "ibm,plb4";
                #address-cells = <2>;