riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
authorConor Dooley <conor.dooley@microchip.com>
Tue, 27 Sep 2022 11:19:17 +0000 (12:19 +0100)
committerConor Dooley <conor.dooley@microchip.com>
Tue, 27 Sep 2022 17:53:58 +0000 (18:53 +0100)
In today's edition of moving things around:

The PCIe root port on PolarFire SoC is more part of the FPGA than of
the Core Complex. It is located on the other side of the chip and,
apart from its interrupts, most of its configuration is determined
by the FPGA bitstream rather. This includes:

- address translation in both directions
- the addresses at which the config and data regions appear to the
  core complex
- the clocks used by the AXI bus
- the plic interrupt used

Moving the PCIe node to the -fabric.dtsi makes it clearer than a
singular configuration for root port is not correct & allows the
base SoC dtsi to be more easily included.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
arch/riscv/boot/dts/microchip/mpfs.dtsi

index eec5aba..688ef0f 100644 (file)
                #clock-cells = <0>;
                clock-frequency = <125000000>;
        };
-};
 
-&pcie {
-       dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
+       pcie: pcie@2000000000 {
+               compatible = "microchip,pcie-host-1.0";
+               #address-cells = <0x3>;
+               #interrupt-cells = <0x1>;
+               #size-cells = <0x2>;
+               device_type = "pci";
+               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+               reg-names = "cfg", "apb";
+               bus-range = <0x0 0x7f>;
+               interrupt-parent = <&plic>;
+               interrupts = <119>;
+               interrupt-map = <0 0 0 1 &pcie_intc 0>,
+                               <0 0 0 2 &pcie_intc 1>,
+                               <0 0 0 3 &pcie_intc 2>,
+                               <0 0 0 4 &pcie_intc 3>;
+               interrupt-map-mask = <0 0 0 7>;
+               clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+               clock-names = "fic0", "fic1", "fic3";
+               ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+               dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
+               msi-parent = <&pcie>;
+               msi-controller;
+               status = "disabled";
+               pcie_intc: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
 };
index 49380c4..67303bc 100644 (file)
                #clock-cells = <0>;
                clock-frequency = <125000000>;
        };
+
+       pcie: pcie@2000000000 {
+               compatible = "microchip,pcie-host-1.0";
+               #address-cells = <0x3>;
+               #interrupt-cells = <0x1>;
+               #size-cells = <0x2>;
+               device_type = "pci";
+               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+               reg-names = "cfg", "apb";
+               bus-range = <0x0 0x7f>;
+               interrupt-parent = <&plic>;
+               interrupts = <119>;
+               interrupt-map = <0 0 0 1 &pcie_intc 0>,
+                               <0 0 0 2 &pcie_intc 1>,
+                               <0 0 0 3 &pcie_intc 2>,
+                               <0 0 0 4 &pcie_intc 3>;
+               interrupt-map-mask = <0 0 0 7>;
+               clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+               clock-names = "fic0", "fic1", "fic3";
+               ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+               msi-parent = <&pcie>;
+               msi-controller;
+               status = "disabled";
+               pcie_intc: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
 };
index 45e3cc6..79fd8df 100644 (file)
                        status = "disabled";
                };
 
-               pcie: pcie@2000000000 {
-                       compatible = "microchip,pcie-host-1.0";
-                       #address-cells = <0x3>;
-                       #interrupt-cells = <0x1>;
-                       #size-cells = <0x2>;
-                       device_type = "pci";
-                       reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
-                       reg-names = "cfg", "apb";
-                       bus-range = <0x0 0x7f>;
-                       interrupt-parent = <&plic>;
-                       interrupts = <119>;
-                       interrupt-map = <0 0 0 1 &pcie_intc 0>,
-                                       <0 0 0 2 &pcie_intc 1>,
-                                       <0 0 0 3 &pcie_intc 2>,
-                                       <0 0 0 4 &pcie_intc 3>;
-                       interrupt-map-mask = <0 0 0 7>;
-                       clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
-                       clock-names = "fic0", "fic1", "fic3";
-                       ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
-                       msi-parent = <&pcie>;
-                       msi-controller;
-                       microchip,axi-m-atr0 = <0x10 0x0>;
-                       status = "disabled";
-                       pcie_intc: legacy-interrupt-controller {
-                               #address-cells = <0>;
-                               #interrupt-cells = <1>;
-                               interrupt-controller;
-                       };
-               };
-
                mbox: mailbox@37020000 {
                        compatible = "microchip,mpfs-mailbox";
                        reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;