select GENERIC_IRQ_SHOW
select GENERIC_PCI_IOMAP
select GENERIC_SMP_IDLE_THREAD
+ select GENERIC_IDLE_POLL_SETUP
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
select HARDIRQS_SW_RESEND
This enables support for systems based on Atmel
AT91RM9200 and AT91SAM9* processors.
- config ARCH_BCM2835
- bool "Broadcom BCM2835 family"
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select ARM_ERRATA_411920
- select ARM_TIMER_SP804
- select CLKDEV_LOOKUP
- select CLKSRC_OF
- select COMMON_CLK
- select CPU_V6
- select GENERIC_CLOCKEVENTS
- select MULTI_IRQ_HANDLER
- select PINCTRL
- select PINCTRL_BCM2835
- select SPARSE_IRQ
- select USE_OF
- help
- This enables support for the Broadcom BCM2835 SoC. This SoC is
- use in the Raspberry Pi, and Roku 2 devices.
-
- config ARCH_CNS3XXX
- bool "Cavium Networks CNS3XXX family"
- select ARM_GIC
- select CPU_V6K
- select GENERIC_CLOCKEVENTS
- select MIGHT_HAVE_CACHE_L2X0
- select MIGHT_HAVE_PCI
- select PCI_DOMAINS if PCI
- help
- Support for Cavium Networks CNS3XXX platform.
-
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
bool "Cortina Systems Gemini"
select ARCH_REQUIRE_GPIOLIB
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_GPIO_H
select CPU_FA526
help
Support for the Cortina Systems Gemini family SoCs
- config ARCH_SIRF
- bool "CSR SiRF"
- select ARCH_REQUIRE_GPIOLIB
- select AUTO_ZRELADDR
- select COMMON_CLK
- select GENERIC_CLOCKEVENTS
- select GENERIC_IRQ_CHIP
- select MIGHT_HAVE_CACHE_L2X0
- select NO_IOPORT
- select PINCTRL
- select PINCTRL_SIRF
- select USE_OF
- help
- Support for CSR SiRFprimaII/Marco/Polo platforms
-
config ARCH_EBSA110
bool "EBSA-110"
select ARCH_USES_GETTIMEOFFSET
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
- config ARCH_MXS
- bool "Freescale MXS-based"
- select ARCH_REQUIRE_GPIOLIB
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select CLKSRC_OF
- select COMMON_CLK
- select GENERIC_CLOCKEVENTS
- select HAVE_CLK_PREPARE
- select MULTI_IRQ_HANDLER
- select PINCTRL
- select SPARSE_IRQ
- select STMP_DEVICE
- select USE_OF
- help
- Support for Freescale MXS-based family of processors
-
config ARCH_NETX
bool "Hilscher NetX based"
select ARM_VIC
help
This enables support for systems based on the Hilscher NetX Soc
-config ARCH_H720X
- bool "Hynix HMS720x-based"
- select ARCH_USES_GETTIMEOFFSET
- select CPU_ARM720T
- select ISA_DMA_API
- help
- This enables support for systems based on the Hynix HMS720x
-
config ARCH_IOP13XX
bool "IOP13xx-based"
depends on MMU
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select NEED_MACH_IO_H
+ select USB_EHCI_BIG_ENDIAN_MMIO
+ select USB_EHCI_BIG_ENDIAN_DESC
help
Support for Intel's IXP4XX (XScale) family of processors.
help
Support for the NXP LPC32XX family of processors
- config ARCH_TEGRA
- bool "NVIDIA Tegra"
- select ARCH_HAS_CPUFREQ
- select ARCH_REQUIRE_GPIOLIB
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select CLKSRC_OF
- select COMMON_CLK
- select GENERIC_CLOCKEVENTS
- select HAVE_CLK
- select HAVE_SMP
- select MIGHT_HAVE_CACHE_L2X0
- select SOC_BUS
- select SPARSE_IRQ
- select USE_OF
- help
- This enables support for NVIDIA Tegra based systems (Tegra APX,
- Tegra 6xx and Tegra 2 series).
-
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
bool "Renesas SH-Mobile / R-Mobile"
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_CLK
select HAVE_MACH_CLKDEV
select HAVE_SMP
help
Support for ST-Ericsson U300 series mobile platforms.
- config ARCH_U8500
- bool "ST-Ericsson U8500 Series"
- depends on MMU
- select ARCH_HAS_CPUFREQ
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select CLKDEV_LOOKUP
- select CPU_V7
- select GENERIC_CLOCKEVENTS
- select HAVE_SMP
- select MIGHT_HAVE_CACHE_L2X0
- select SPARSE_IRQ
- help
- Support for ST-Ericsson's Ux500 architecture
-
- config ARCH_NOMADIK
- bool "STMicroelectronics Nomadik"
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select ARM_VIC
- select CLKSRC_NOMADIK_MTU
- select COMMON_CLK
- select CPU_ARM926T
- select GENERIC_CLOCKEVENTS
- select MIGHT_HAVE_CACHE_L2X0
- select USE_OF
- select PINCTRL
- select PINCTRL_STN8815
- select SPARSE_IRQ
- help
- Support for the Nomadik platform by ST-Ericsson
-
- config PLAT_SPEAR
- bool "ST SPEAr"
- select ARCH_HAS_CPUFREQ
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select COMMON_CLK
- select GENERIC_CLOCKEVENTS
- select HAVE_CLK
- help
- Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
-
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
source "arch/arm/mach-bcm/Kconfig"
+ source "arch/arm/mach-bcm2835/Kconfig"
+
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
-source "arch/arm/mach-h720x/Kconfig"
-
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
- source "arch/arm/plat-spear/Kconfig"
+ source "arch/arm/mach-spear/Kconfig"
source "arch/arm/mach-s3c24xx/Kconfig"
config ARM_TIMER_SP804
bool
select CLKSRC_MMIO
- select HAVE_SCHED_CLOCK
source arch/arm/mm/Kconfig
default 8
config IWMMXT
- bool "Enable iWMMXt support"
+ bool "Enable iWMMXt support" if !CPU_PJ4
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
- default y if PXA27x || PXA3xx || ARCH_MMP
+ default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
to deadlock. This workaround puts DSB before executing ISB if
an abort may occur on cache maintenance.
+config ARM_ERRATA_798181
+ bool "ARM errata: TLBI/DSB failure on Cortex-A15"
+ depends on CPU_V7 && SMP
+ help
+ On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
+ adequately shooting down all use of the old entries. This
+ option enables the Linux kernel workaround for this erratum
+ which sends an IPI to the CPUs that are running the same ASID
+ as the one being invalidated.
+
endmenu
source "arch/arm/common/Kconfig"
depends on GENERIC_CLOCKEVENTS
depends on HAVE_SMP
depends on MMU
- select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
select USE_GENERIC_SMP_HELPERS
help
This enables support for systems with more than one CPU. If you have
bool "Use local timer interrupts"
depends on SMP
default y
- select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if SOC_OMAP5
- default 355 if ARCH_U8500
+ default 392 if ARCH_U8500
default 288 if ARCH_VT8500 || ARCH_SUNXI
default 264 if MACH_H4700
default 0
menu "CPU Power Management"
if ARCH_HAS_CPUFREQ
-
source "drivers/cpufreq/Kconfig"
-config CPU_FREQ_IMX
- tristate "CPUfreq driver for i.MX CPUs"
- depends on ARCH_MXC && CPU_FREQ
- select CPU_FREQ_TABLE
- help
- This enables the CPUfreq driver for i.MX CPUs.
-
-config CPU_FREQ_SA1100
- bool
-
-config CPU_FREQ_SA1110
- bool
-
-config CPU_FREQ_INTEGRATOR
- tristate "CPUfreq driver for ARM Integrator CPUs"
- depends on ARCH_INTEGRATOR && CPU_FREQ
- default y
- help
- This enables the CPUfreq driver for ARM Integrator CPUs.
-
- For details, take a look at <file:Documentation/cpu-freq>.
-
- If in doubt, say Y.
-
-config CPU_FREQ_PXA
- bool
- depends on CPU_FREQ && ARCH_PXA && PXA25x
- default y
- select CPU_FREQ_DEFAULT_GOV_USERSPACE
- select CPU_FREQ_TABLE
-
config CPU_FREQ_S3C
bool
help
machine-$(CONFIG_ARCH_EBSA110) += ebsa110
machine-$(CONFIG_ARCH_EP93XX) += ep93xx
machine-$(CONFIG_ARCH_GEMINI) += gemini
-machine-$(CONFIG_ARCH_H720X) += h720x
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
machine-$(CONFIG_ARCH_W90X900) += w90x900
machine-$(CONFIG_FOOTBRIDGE) += footbridge
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
- machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
- machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
- machine-$(CONFIG_MACH_SPEAR600) += spear6xx
+ machine-$(CONFIG_PLAT_SPEAR) += spear
machine-$(CONFIG_ARCH_VIRT) += virt
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_SUNXI) += sunxi
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += samsung
plat-$(CONFIG_PLAT_S5P) += samsung
- plat-$(CONFIG_PLAT_SPEAR) += spear
plat-$(CONFIG_PLAT_VERSATILE) += versatile
ifeq ($(CONFIG_ARCH_EBSA110),y)
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
CONFIG_JUMP_LABEL=y
+ CONFIG_ARCH_MULTI_V6=y
+ # CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_BCM2835=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_TTY_PRINTK=y
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM2835=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_BCM2835=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM2835=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_STRICT_DEVMEM=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
-# CONFIG_XZ_DEC_X86 is not set
-# CONFIG_XZ_DEC_POWERPC is not set
-# CONFIG_XZ_DEC_IA64 is not set
# CONFIG_XZ_DEC_ARM is not set
# CONFIG_XZ_DEC_ARMTHUMB is not set
-# CONFIG_XZ_DEC_SPARC is not set
CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
+ # CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MXS=y
- CONFIG_MACH_MXS_DT=y
# CONFIG_ARM_THUMB is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_MICREL_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_STMP3XXX_RTC_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_FB=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_PHY=y
CONFIG_USB_MXS_PHY=y
CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_MXS=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
-#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
-#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
-#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
-#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
-#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
-#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
#define SMC_MEMC_STATUS_OFFSET 0x000
#define SMC_MEMIF_CFG_OFFSET 0x004
#define SMC_PCELL_ID_3_OFFSET 0xFFC
#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
-#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
-#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
-#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
#define RTC_SEC_OFFSET 0x00
#define RTC_MIN_OFFSET 0x04
#define RTC_INTR_STS_OFFSET 0x34
#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
-#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
+#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
-#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
+#define CNS3XXX_PM_BASE_VIRT 0xFB001000
#define PM_CLK_GATE_OFFSET 0x00
#define PM_SOFT_RST_OFFSET 0x04
#define PM_PLL_HM_PD_OFFSET 0x1C
#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
-#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
+#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
-#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
-#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
-#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
-#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
-#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
-#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
-#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
+#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
#define TIMER1_COUNTER_OFFSET 0x00
#define TIMER1_AUTO_RELOAD_OFFSET 0x04
#define TIMER_FREERUN_CONTROL_OFFSET 0x44
#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
-#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
-#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
-#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
-#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
-#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
#define CNS3XXX_SATA2_SIZE SZ_16M
-#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
-#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
-#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
-#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
-#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
-#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
* Testchip peripheral and fpga gic regions
*/
#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
-#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
+#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
-#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
+#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
-#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
+#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
-#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
+#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
-#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
/*
* Misc block
/*
* ARM11 MPCore interrupt sources (primary GIC)
*/
+ #define IRQ_TC11MP_GIC_START 32
+
#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
- #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
- #undef NR_IRQS
- #define NR_IRQS NR_IRQS_CNS3XXX
- #endif
-
#endif /* __MACH_BOARD_CNS3XXX_H */
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
+ #include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/usb/ehci_pdriver.h>
+ #include <linux/usb/ohci_pdriver.h>
+ #include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/cache-l2x0.h>
- #include <mach/cns3xxx.h>
+ #include "cns3xxx.h"
#include "core.h"
+ #include "pm.h"
static struct map_desc cns3xxx_io_desc[] __initdata = {
{
- .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
- .length = SZ_4K,
+ .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
+ .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
+ .length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = CNS3XXX_GPIOA_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_GPIOB_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
.virtual = CNS3XXX_MISC_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
.length = SZ_4K,
}
#endif /* CONFIG_CACHE_L2X0 */
+
+ static int csn3xxx_usb_power_on(struct platform_device *pdev)
+ {
+ /*
+ * EHCI and OHCI share the same clock and power,
+ * resetting twice would cause the 1st controller been reset.
+ * Therefore only do power up at the first up device, and
+ * power down at the last down device.
+ *
+ * Set USB AHB INCR length to 16
+ */
+ if (atomic_inc_return(&usb_pwr_ref) == 1) {
+ cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
+ cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+ cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
+ __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
+ MISC_CHIP_CONFIG_REG);
+ }
+
+ return 0;
+ }
+
+ static void csn3xxx_usb_power_off(struct platform_device *pdev)
+ {
+ /*
+ * EHCI and OHCI share the same clock and power,
+ * resetting twice would cause the 1st controller been reset.
+ * Therefore only do power up at the first up device, and
+ * power down at the last down device.
+ */
+ if (atomic_dec_return(&usb_pwr_ref) == 0)
+ cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+ }
+
+ static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
+ .power_on = csn3xxx_usb_power_on,
+ .power_off = csn3xxx_usb_power_off,
+ };
+
+ static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
+ .num_ports = 1,
+ .power_on = csn3xxx_usb_power_on,
+ .power_off = csn3xxx_usb_power_off,
+ };
+
+ static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
+ { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
+ { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
+ { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
+ { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
+ {},
+ };
+
+ static void __init cns3xxx_init(void)
+ {
+ struct device_node *dn;
+
+ cns3xxx_l2x0_init();
+
+ dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
+ if (of_device_is_available(dn)) {
+ u32 tmp;
+
+ tmp = __raw_readl(MISC_SATA_POWER_MODE);
+ tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+ tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+ __raw_writel(tmp, MISC_SATA_POWER_MODE);
+
+ /* Enable SATA PHY */
+ cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+ cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+
+ /* Enable SATA Clock */
+ cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+
+ /* De-Asscer SATA Reset */
+ cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+ }
+
+ dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
+ if (of_device_is_available(dn)) {
+ u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+ u32 gpioa_pins = __raw_readl(gpioa);
+
+ /* MMC/SD pins share with GPIOA */
+ gpioa_pins |= 0x1fff0004;
+ __raw_writel(gpioa_pins, gpioa);
+
+ cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+ cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+ }
+
+ pm_power_off = cns3xxx_power_off;
+
+ of_platform_populate(NULL, of_default_bus_match_table,
+ cns3xxx_auxdata, NULL);
+ }
+
+ static const char *cns3xxx_dt_compat[] __initdata = {
+ "cavium,cns3410",
+ "cavium,cns3420",
+ NULL,
+ };
+
+ DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
+ .dt_compat = cns3xxx_dt_compat,
+ .nr_irqs = NR_IRQS_CNS3XXX,
+ .map_io = cns3xxx_map_io,
+ .init_irq = cns3xxx_init_irq,
+ .init_time = cns3xxx_timer_init,
+ .init_machine = cns3xxx_init,
+ .restart = cns3xxx_restart,
+ MACHINE_END
config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4"
default y
+ select HAVE_ARM_SCU if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
+ select HAVE_ARM_SCU if SMP
select HAVE_SMP
help
Samsung EXYNOS5 (Cortex-A15) SoC based systems
bool "SAMSUNG EXYNOS5440"
default y
depends on ARCH_EXYNOS5
+ select ARCH_HAS_OPP
select ARM_ARCH_TIMER
select AUTO_ZRELADDR
select PINCTRL
select PINCTRL_EXYNOS5440
+ select PM_OPP
help
Enable EXYNOS5440 SoC support
help
Use MCT (Multi Core Timer) as kernel timers
+ config EXYNOS_ATAGS
+ bool "ATAGS based boot for EXYNOS (deprecated)"
+ depends on !ARCH_MULTIPLATFORM
+ depends on ATAGS
+ default y
+ help
+ The EXYNOS platform is moving towards being completely probed
+ through device tree. This enables support for board files using
+ the traditional ATAGS boot format.
+ Note that this option is not available for multiplatform builds.
+
+ if EXYNOS_ATAGS
+
config EXYNOS_DEV_DMA
bool
help
help
Compile in platform device definitions for AHCI
-config EXYNOS_DEV_DRM
- bool
- help
- Compile in platform device definitions for core DRM device
-
config EXYNOS4_SETUP_FIMD0
bool
help
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
- select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
select S3C24XX_PWM
select S3C_DEV_HSMMC
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
- select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
- select HAVE_SCHED_CLOCK
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
- select EXYNOS_DEV_DRM
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
- select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
select S3C24XX_PWM
select S3C_DEV_HSMMC
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
- select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
select S3C24XX_PWM
select S3C_DEV_HSMMC2
Machine support for Samsung SMDK4412
endif
+ endif
+
comment "Flattened Device Tree based board for EXYNOS SoCs"
config MACH_EXYNOS4_DT
depends on ARCH_EXYNOS4
select ARM_AMBA
select CPU_EXYNOS4210
- select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+ select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
select PINCTRL
select PINCTRL_EXYNOS
select USE_OF
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/hdmi.h>
#include <mach/map.h>
+ #include <mach/irqs.h>
#include <drm/exynos_drm.h>
#include "common.h"
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/clock.h>
#include <plat/hdmi.h>
+ #include <mach/irqs.h>
#include <mach/map.h>
#include <drm/exynos_drm.h>
config ARCH_MX1
bool
-config MACH_MX21
- bool
-
config ARCH_MX25
bool
config MACH_MX27
bool
-config ARCH_MX5
- bool
-
-config ARCH_MX51
- bool
-
-config ARCH_MX53
- bool
-
config SOC_IMX1
bool
select ARCH_MX1
select COMMON_CLK
select CPU_ARM926T
select IMX_HAVE_IOMUX_V1
- select MACH_MX21
select MXC_AVIC
config SOC_IMX25
config SOC_IMX5
bool
select ARCH_HAS_CPUFREQ
- select ARCH_MX5
select ARCH_MXC_IOMUX_V3
select COMMON_CLK
select CPU_V7
config SOC_IMX51
bool
- select ARCH_MX5
- select ARCH_MX51
+ select HAVE_IMX_SRC
select PINCTRL
select PINCTRL_IMX51
select SOC_IMX5
config SOC_IMX53
bool "i.MX53 support"
- select ARCH_MX5
- select ARCH_MX53
select HAVE_CAN_FLEXCAN if CAN
+ select HAVE_IMX_SRC
select IMX_HAVE_PLATFORM_IMX2_WDT
select PINCTRL
select PINCTRL_IMX53
select ARM_GIC
select COMMON_CLK
select CPU_V7
- select HAVE_ARM_SCU
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_CAN_FLEXCAN if CAN
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
- if ARCH_MXS
-
config SOC_IMX23
bool
select ARM_AMBA
+ select ARM_CPU_SUSPEND if PM
select CPU_ARM926T
select HAVE_PWM
select PINCTRL_IMX23
config SOC_IMX28
bool
select ARM_AMBA
+ select ARM_CPU_SUSPEND if PM
select CPU_ARM926T
select HAVE_CAN_FLEXCAN if CAN
select HAVE_PWM
select PINCTRL_IMX28
- comment "MXS platforms:"
-
- config MACH_MXS_DT
- bool "Support MXS platforms from device tree"
+ config ARCH_MXS
+ bool "Freescale MXS (i.MX23, i.MX28) support"
+ depends on ARCH_MULTI_V5
+ select ARCH_REQUIRE_GPIOLIB
+ select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
+ select CLKSRC_OF
+ select GENERIC_CLOCKEVENTS
+ select HAVE_CLK_PREPARE
+ select PINCTRL
select SOC_IMX23
select SOC_IMX28
+ select STMP_DEVICE
help
- Include support for Freescale MXS platforms(i.MX23 and i.MX28)
- using the device tree for discovery
-
- endif
+ Support for Freescale MXS-based family of processors
select OMAP_DM_TIMER
select PINCTRL
select PROC_DEVICETREE if PROC_FS
+ select SOC_BUS
select SPARSE_IRQ
select USE_OF
help
config ARCH_OMAP2
bool "TI OMAP2"
depends on ARCH_OMAP2PLUS
+ depends on ARCH_MULTI_V6
default y
select CPU_V6
select MULTI_IRQ_HANDLER
config ARCH_OMAP3
bool "TI OMAP3"
depends on ARCH_OMAP2PLUS
+ depends on ARCH_MULTI_V7
default y
select ARCH_HAS_OPP
select ARM_CPU_SUSPEND if PM
bool "TI OMAP4"
default y
depends on ARCH_OMAP2PLUS
+ depends on ARCH_MULTI_V7
select ARCH_HAS_OPP
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select CACHE_L2X0
select CPU_V7
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select LOCAL_TIMERS if SMP
select OMAP_INTERCONNECT
select PM_RUNTIME if CPU_IDLE
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select COMMON_CLK
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
config SOC_OMAP5
bool "TI OMAP5"
+ depends on ARCH_MULTI_V7
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select CPU_V7
config SOC_AM33XX
bool "AM33XX support"
+ depends on ARCH_MULTI_V7
default y
select ARM_CPU_SUSPEND if PM
select CPU_V7
config OMAP4_ERRATA_I688
bool "OMAP4 errata: Async Bridge Corruption"
- depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM
+ depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
select ARCH_HAS_BARRIERS
help
If a data is stalled inside asynchronous bridge because of back
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
- #include <mach/map.h>
#include "common.h"
static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_scu.h>
#include <mach/spear.h>
- #include <mach/generic.h>
+ #include "generic.h"
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
- if ARCH_TEGRA
+ config ARCH_TEGRA
+ bool "NVIDIA Tegra" if ARCH_MULTI_V7
+ select ARCH_HAS_CPUFREQ
+ select ARCH_REQUIRE_GPIOLIB
+ select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
+ select CLKSRC_OF
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if LOCAL_TIMERS
+ select HAVE_CLK
+ select HAVE_SMP
+ select MIGHT_HAVE_CACHE_L2X0
+ select SOC_BUS
+ select SPARSE_IRQ
+ select USE_OF
+ help
+ This enables support for NVIDIA Tegra based systems.
- comment "NVIDIA Tegra options"
+ menu "NVIDIA Tegra options"
+ depends on ARCH_TEGRA
config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_ERRATA_720789
- select ARM_ERRATA_742230 if SMP
- select ARM_ERRATA_751472
select ARM_ERRATA_754327 if SMP
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB
- select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select USB_ULPI if USB_PHY
+ select USB_ULPI_VIEWPORT if USB_PHY
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
- select ARM_ERRATA_743622
- select ARM_ERRATA_751472
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select PINCTRL_TEGRA30
select PL310_ERRATA_769419 if CACHE_L2X0
select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB
- select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select USB_ULPI if USB_PHY
+ select USB_ULPI_VIEWPORT if USB_PHY
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency"
- endif
+ endmenu
+ asflags-y += -march=armv7-a
+
obj-y += common.o
obj-y += io.o
obj-y += irq.o
endif
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
obj-$(CONFIG_TEGRA_PCI) += pcie.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/clk/tegra.h>
-
- #include <mach/powergate.h>
+ #include <linux/tegra-powergate.h>
#include "fuse.h"
#include "iomap.h"
if (status == new_state) {
spin_unlock_irqrestore(&tegra_powergate_lock, flags);
- return -EINVAL;
+ return 0;
}
pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
err_power:
return ret;
}
+EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
int tegra_cpu_powergate_id(int cpuid)
{
#include <linux/platform_data/dma-ste-dma40.h>
#include <asm/mach-types.h>
- #include <mach/devices.h>
- #include <mach/hardware.h>
+ #include "devices.h"
+ #include "db8500-regs.h"
#include "devices-db8500.h"
#include "board-mop500.h"
#include "ste-dma40-db8500.h"
* SDI 0 (MicroSD slot)
*/
-/* GPIO pins used by the sdi0 level shifter */
-static int sdi0_en = -1;
-static int sdi0_vsel = -1;
-
-static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
-{
- switch (ios->power_mode) {
- case MMC_POWER_UP:
- case MMC_POWER_ON:
- /*
- * Level shifter voltage should depend on vdd to when deciding
- * on either 1.8V or 2.9V. Once the decision has been made the
- * level shifter must be disabled and re-enabled with a changed
- * select signal in order to switch the voltage. Since there is
- * no framework support yet for indicating 1.8V in vdd, use the
- * default 2.9V.
- */
- gpio_direction_output(sdi0_vsel, 0);
- gpio_direction_output(sdi0_en, 1);
- break;
- case MMC_POWER_OFF:
- gpio_direction_output(sdi0_vsel, 0);
- gpio_direction_output(sdi0_en, 0);
- break;
- }
-
- return 0;
-}
-
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
#endif
struct mmci_platform_data mop500_sdi0_data = {
- .ios_handler = mop500_sdi0_ios_handler,
.ocr_mask = MMC_VDD_29_30,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA |
static void sdi0_configure(struct device *parent)
{
- int ret;
-
- ret = gpio_request(sdi0_en, "level shifter enable");
- if (!ret)
- ret = gpio_request(sdi0_vsel,
- "level shifter 1v8-3v select");
-
- if (ret) {
- pr_warning("unable to config sdi0 gpios for level shifter.\n");
- return;
- }
-
- /* Select the default 2.9V and enable level shifter */
- gpio_direction_output(sdi0_vsel, 0);
- gpio_direction_output(sdi0_en, 1);
-
/* Add the device, force v2 to subrevision 1 */
db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
}
void mop500_sdi_tc35892_init(struct device *parent)
{
mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
- sdi0_en = GPIO_SDMMC_EN;
- sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
sdi0_configure(parent);
}
/* External Micro SD slot */
mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
mop500_sdi0_data.cd_invert = true;
- sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
- sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
sdi0_configure(parent);
}
db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/* External Micro SD slot */
mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
- sdi0_en = HREFV60_SDMMC_EN_GPIO;
- sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
sdi0_configure(parent);
/* WLAN SDIO channel */
db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/platform_data/i2c-nomadik.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/regulator/ab8500.h>
#include <linux/regulator/fixed.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
#include <linux/mfd/tc3589x.h>
#include <linux/mfd/tps6105x.h>
#include <linux/mfd/abx500/ab8500-gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
- #include <mach/hardware.h>
- #include <mach/setup.h>
- #include <mach/devices.h>
- #include <mach/irqs.h>
+ #include "setup.h"
+ #include "devices.h"
+ #include "irqs.h"
#include <linux/platform_data/crypto-ux500.h>
#include "ste-dma40-db8500.h"
+ #include "db8500-regs.h"
#include "devices-db8500.h"
#include "board-mop500.h"
#include "board-mop500-regulators.h"
},
};
+/* Dynamically populated. */
+static struct gpio sdi0_reg_gpios[] = {
+ { 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" },
+};
+
+static struct gpio_regulator_state sdi0_reg_states[] = {
+ { .value = 2900000, .gpios = (0 << 0) },
+ { .value = 1800000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config sdi0_reg_info = {
+ .supply_name = "ext-mmc-level-shifter",
+ .gpios = sdi0_reg_gpios,
+ .nr_gpios = ARRAY_SIZE(sdi0_reg_gpios),
+ .states = sdi0_reg_states,
+ .nr_states = ARRAY_SIZE(sdi0_reg_states),
+ .type = REGULATOR_VOLTAGE,
+ .enable_high = 1,
+ .enabled_at_boot = 0,
+ .init_data = &sdi0_reg_init_data,
+ .startup_delay = 100,
+};
+
+static struct platform_device sdi0_regulator = {
+ .name = "gpio-regulator",
+ .id = -1,
+ .dev = {
+ .platform_data = &sdi0_reg_info,
+ },
+};
+
static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
.gpio_base = MOP500_AB8500_PIN_GPIO(1),
};
struct ab8500_platform_data ab8500_platdata = {
.irq_base = MOP500_AB8500_IRQ_BASE,
- .regulator_reg_init = ab8500_regulator_reg_init,
- .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init),
- .regulator = ab8500_regulators,
- .num_regulator = ARRAY_SIZE(ab8500_regulators),
+ .regulator = &ab8500_regulator_plat_data,
.gpio = &ab8500_gpio_pdata,
.codec = &ab8500_codec_pdata,
};
- /*
- * Thermal Sensor
- */
-
- static struct resource db8500_thsens_resources[] = {
- {
- .name = "IRQ_HOTMON_LOW",
- .start = IRQ_PRCMU_HOTMON_LOW,
- .end = IRQ_PRCMU_HOTMON_LOW,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "IRQ_HOTMON_HIGH",
- .start = IRQ_PRCMU_HOTMON_HIGH,
- .end = IRQ_PRCMU_HOTMON_HIGH,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- static struct db8500_thsens_platform_data db8500_thsens_data = {
- .trip_points[0] = {
- .temp = 70000,
- .type = THERMAL_TRIP_ACTIVE,
- .cdev_name = {
- [0] = "thermal-cpufreq-0",
- },
- },
- .trip_points[1] = {
- .temp = 75000,
- .type = THERMAL_TRIP_ACTIVE,
- .cdev_name = {
- [0] = "thermal-cpufreq-0",
- },
- },
- .trip_points[2] = {
- .temp = 80000,
- .type = THERMAL_TRIP_ACTIVE,
- .cdev_name = {
- [0] = "thermal-cpufreq-0",
- },
- },
- .trip_points[3] = {
- .temp = 85000,
- .type = THERMAL_TRIP_CRITICAL,
- },
- .num_trips = 4,
- };
-
- static struct platform_device u8500_thsens_device = {
- .name = "db8500-thermal",
- .resource = db8500_thsens_resources,
- .num_resources = ARRAY_SIZE(db8500_thsens_resources),
- .dev = {
- .platform_data = &db8500_thsens_data,
- },
- };
-
static struct platform_device u8500_cpufreq_cooling_device = {
.name = "db8500-cpufreq-cooling",
};
regulator_put(prox_regulator);
}
+void mop500_snowball_ethernet_clock_enable(void)
+{
+ struct clk *clk;
+
+ clk = clk_get_sys("fsmc", NULL);
+ if (!IS_ERR(clk))
+ clk_prepare_enable(clk);
+}
+
static struct cryp_platform_data u8500_cryp1_platform_data = {
.mem_to_engine = {
.dir = STEDMA40_MEM_TO_PERIPH,
/* add any platform devices here - TODO */
static struct platform_device *mop500_platform_devs[] __initdata = {
&mop500_gpio_keys_device,
+ &sdi0_regulator,
};
#ifdef CONFIG_STE_DMA40
&snowball_key_dev,
&snowball_sbnet_dev,
&snowball_gpio_en_3v3_regulator_dev,
- &u8500_thsens_device,
&u8500_cpufreq_cooling_device,
+ &sdi0_regulator,
};
static void __init mop500_init_machine(void)
platform_device_register(&db8500_prcmu_device);
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+ sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN;
+ sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
+
mop500_pinmaps_init();
parent = u8500_init_devices(&ab8500_platdata);
int i;
platform_device_register(&db8500_prcmu_device);
+
+ sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;
+ sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
+
snowball_pinmaps_init();
parent = u8500_init_devices(&ab8500_platdata);
mop500_audio_init(parent);
mop500_uart_init(parent);
+ mop500_snowball_ethernet_clock_enable();
+
/* This board has full regulator constraints */
regulator_has_full_constraints();
}
*/
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+ sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO;
+ sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
+
hrefv60_pinmaps_init();
parent = u8500_init_devices(&ab8500_platdata);
#define __BOARD_MOP500_H
/* For NOMADIK_NR_GPIO */
- #include <mach/irqs.h>
- #include <mach/msp.h>
+ #include "irqs.h"
+ #include <linux/platform_data/asoc-ux500-msp.h>
#include <linux/amba/mmci.h>
/* Snowball specific GPIO assignments, this board has no GPIO expander */
void __init snowball_pinmaps_init(void);
void __init hrefv60_pinmaps_init(void);
void mop500_audio_init(struct device *parent);
+void mop500_snowball_ethernet_clock_enable(void);
int __init mop500_uib_init(void);
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
- #include <mach/hardware.h>
+ #include "db8500-regs.h"
#include "id.h"
static void __iomem *l2x0_base;
/* Unlock before init */
ux500_l2x0_unlock();
- /* DB9540's L2 has 128KB way size */
- if (cpu_is_u9540())
+ /* DBx540's L2 has 128KB way size */
+ if (cpu_is_ux540_family())
/* 128KB way size */
aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
else
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
- #include <mach/hardware.h>
- #include <mach/setup.h>
- #include <mach/devices.h>
- #include <mach/db8500-regs.h>
- #include <mach/irqs.h>
+ #include "setup.h"
+ #include "devices.h"
+ #include "irqs.h"
#include "devices-db8500.h"
#include "ste-dma40-db8500.h"
-
+ #include "db8500-regs.h"
#include "board-mop500.h"
#include "id.h"
iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
else
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
-
- _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
}
static struct resource db8500_pmu_resources[] = {
OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
&db8500_prcmu_pdata),
+ OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
/* Requires device name bindings. */
OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
"pinctrl-db8500", NULL),
/* Pinmaps must be in place before devices register */
if (of_machine_is_compatible("st-ericsson,mop500"))
mop500_pinmaps_init();
- else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
+ else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
snowball_pinmaps_init();
- else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
+ mop500_snowball_ethernet_clock_enable();
+ } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
hrefv60_pinmaps_init();
else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
/* TODO: Add pinmaps for ccu9540 board. */
#include <linux/module.h>
#include <linux/cpuidle.h>
-#include <linux/clockchips.h>
#include <linux/spinlock.h>
#include <linux/atomic.h>
#include <linux/smp.h>
#include <linux/mfd/dbx500-prcmu.h>
+ #include <linux/platform_data/arm-ux500-pm.h>
#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
+ #include "db8500-regs.h"
+
static atomic_t master = ATOMIC_INIT(0);
static DEFINE_SPINLOCK(master_lock);
-static DEFINE_PER_CPU(struct cpuidle_device, ux500_cpuidle_device);
static inline int ux500_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
int this_cpu = smp_processor_id();
bool recouple = false;
- clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &this_cpu);
-
if (atomic_inc_return(&master) == num_online_cpus()) {
/* With this lock, we prevent the other cpu to exit and enter
spin_unlock(&master_lock);
}
- clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &this_cpu);
-
return index;
}
static struct cpuidle_driver ux500_idle_driver = {
.name = "ux500_idle",
.owner = THIS_MODULE,
- .en_core_tk_irqen = 1,
.states = {
ARM_CPUIDLE_WFI_STATE,
{
.enter = ux500_enter_idle,
.exit_latency = 70,
.target_residency = 260,
- .flags = CPUIDLE_FLAG_TIME_VALID,
+ .flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_TIMER_STOP,
.name = "ApIdle",
.desc = "ARM Retention",
},
.state_count = 2,
};
-/*
- * For each cpu, setup the broadcast timer because we will
- * need to migrate the timers for the states >= ApIdle.
- */
-static void ux500_setup_broadcast_timer(void *arg)
-{
- int cpu = smp_processor_id();
- clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
-}
-
int __init ux500_idle_init(void)
{
- /* Configure wake up reasons */
- int ret, cpu;
- struct cpuidle_device *device;
-
+ /* Configure wake up reasons */
prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
PRCMU_WAKEUP(ABB));
- /*
- * Configure the timer broadcast for each cpu, that must
- * be done from the cpu context, so we use a smp cross
- * call with 'on_each_cpu'.
- */
- on_each_cpu(ux500_setup_broadcast_timer, NULL, 1);
-
- ret = cpuidle_register_driver(&ux500_idle_driver);
- if (ret) {
- printk(KERN_ERR "failed to register ux500 idle driver\n");
- return ret;
- }
-
- for_each_online_cpu(cpu) {
- device = &per_cpu(ux500_cpuidle_device, cpu);
- device->cpu = cpu;
- ret = cpuidle_register_device(device);
- if (ret) {
- printk(KERN_ERR "Failed to register cpuidle "
- "device for cpu%d\n", cpu);
- goto out_unregister;
- }
- }
-out:
- return ret;
-
-out_unregister:
- for_each_online_cpu(cpu) {
- device = &per_cpu(ux500_cpuidle_device, cpu);
- cpuidle_unregister_device(device);
- }
-
- cpuidle_unregister_driver(&ux500_idle_driver);
- goto out;
+ return cpuidle_register(&ux500_idle_driver, NULL);
}
device_initcall(ux500_idle_init);
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
- #include <mach/hardware.h>
- #include <mach/setup.h>
+ #include "setup.h"
+ #include "db8500-regs.h"
#include "id.h"
/* This is called from headsmp.S to wakeup the secondary core */
static void __cpuinit ux500_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
select COMMON_CLK_VERSATILE
select CPU_V7
select GENERIC_CLOCKEVENTS
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_CLK
select HAVE_PATA_PLATFORM
select HAVE_SMP
select NO_IOPORT
select PLAT_VERSATILE
select PLAT_VERSATILE_CLCD
+ select POWER_RESET
+ select POWER_RESET_VEXPRESS
+ select POWER_SUPPLY
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select VEXPRESS_CONFIG
help
* published by the Free Software Foundation.
*/
+#include <linux/amba/pl330.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
}
#endif /* CONFIG_PLAT_S3C24XX */
- /* MFC */
-
- #ifdef CONFIG_S5P_DEV_MFC
- static struct resource s5p_mfc_resource[] = {
- [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
- [1] = DEFINE_RES_IRQ(IRQ_MFC),
- };
-
- struct platform_device s5p_device_mfc = {
- .name = "s5p-mfc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s5p_mfc_resource),
- .resource = s5p_mfc_resource,
- };
-
- /*
- * MFC hardware has 2 memory interfaces which are modelled as two separate
- * platform devices to let dma-mapping distinguish between them.
- *
- * MFC parent device (s5p_device_mfc) must be registered before memory
- * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
- */
-
- struct platform_device s5p_device_mfc_l = {
- .name = "s5p-mfc-l",
- .id = -1,
- .dev = {
- .parent = &s5p_device_mfc.dev,
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- };
-
- struct platform_device s5p_device_mfc_r = {
- .name = "s5p-mfc-r",
- .id = -1,
- .dev = {
- .parent = &s5p_device_mfc.dev,
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- };
-
- #endif /* CONFIG_S5P_DEV_MFC */
-
/* MIPI CSIS */
#ifdef CONFIG_S5P_DEV_CSIS0
pd.num_cs = num_cs;
pd.src_clk_nr = src_clk_nr;
pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
+#ifdef CONFIG_PL330_DMA
+ pd.filter = pl330_filter;
+#endif
s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
}
pd.num_cs = num_cs;
pd.src_clk_nr = src_clk_nr;
pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
+#ifdef CONFIG_PL330_DMA
+ pd.filter = pl330_filter;
+#endif
s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
}
pd.num_cs = num_cs;
pd.src_clk_nr = src_clk_nr;
pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
+#ifdef CONFIG_PL330_DMA
+ pd.filter = pl330_filter;
+#endif
s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
}
#ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__
+ #include <linux/platform_data/mmc-sdhci-s3c.h>
#include <plat/devs.h>
- struct platform_device;
- struct mmc_host;
- struct mmc_card;
- struct mmc_ios;
-
- enum cd_types {
- S3C_SDHCI_CD_INTERNAL, /* use mmc internal CD line */
- S3C_SDHCI_CD_EXTERNAL, /* use external callback */
- S3C_SDHCI_CD_GPIO, /* use external gpio pin for CD line */
- S3C_SDHCI_CD_NONE, /* no CD line, use polling to detect card */
- S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
- };
-
- /**
- * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
- * @max_width: The maximum number of data bits supported.
- * @host_caps: Standard MMC host capabilities bit field.
- * @host_caps2: The second standard MMC host capabilities bit field.
- * @cd_type: Type of Card Detection method (see cd_types enum above)
- * @ext_cd_init: Initialize external card detect subsystem. Called on
- * sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
- * notify_func argument is a callback to the sdhci-s3c driver
- * that triggers the card detection event. Callback arguments:
- * dev is pointer to platform device of the host controller,
- * state is new state of the card (0 - removed, 1 - inserted).
- * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on
- * sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL.
- * notify_func argument is the same callback as for ext_cd_init.
- * @ext_cd_gpio: gpio pin used for external CD line, valid only if
- * cd_type == S3C_SDHCI_CD_GPIO
- * @ext_cd_gpio_invert: invert values for external CD gpio line
- * @cfg_gpio: Configure the GPIO for a specific card bit-width
- *
- * Initialisation data specific to either the machine or the platform
- * for the device driver to use or call-back when configuring gpio or
- * card speed information.
- */
- struct s3c_sdhci_platdata {
- unsigned int max_width;
- unsigned int host_caps;
- unsigned int host_caps2;
- unsigned int pm_caps;
- enum cd_types cd_type;
-
- int ext_cd_gpio;
- bool ext_cd_gpio_invert;
- int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
- int state));
- int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
- int state));
-
- void (*cfg_gpio)(struct platform_device *dev, int width);
- };
-
/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
* @pd: The default platform data for this device.
* @set: Pointer to the platform data to fill in.
/* S5P64X0 SDHCI setup */
-#ifdef CONFIG_S5P64X0_SETUP_SDHCI
+#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO
static inline void s5p64x0_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
static inline void s5p6440_default_sdhci2(void) { }
static inline void s5p6450_default_sdhci2(void) { }
-#endif /* CONFIG_S5P64X0_SETUP_SDHCI */
+#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */
/* S5PC100 SDHCI setup */
break;
}
}
-
#endif /* __PLAT_S3C_SDHCI_H */
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <mach/map.h>
+ #include <mach/irqs.h>
#include <plat/cpu.h>
#include <plat/irq-vic-timer.h>
#include <plat/regs-timer.h>
-#include <asm/mach/irq.h>
-
static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/spinlock_types.h>
- #include <mach/spear.h>
#include "clk.h"
/* Clock Configuration Registers */
- #define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
+ #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
#define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
#define SPEAR1340_HCLK_SRC_SEL_MASK 1
#define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
#define SPEAR1340_SCLK_SRC_SEL_MASK 3
/* PLL related registers and bit values */
- #define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
+ #define SPEAR1340_PLL_CFG (misc_base + 0x210)
/* PLL_CFG bit values */
#define SPEAR1340_CLCD_SYNT_CLK_MASK 1
#define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
#define SPEAR1340_PLL2_CLK_SHIFT 22
#define SPEAR1340_PLL1_CLK_SHIFT 20
- #define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
- #define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
- #define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
- #define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
- #define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
- #define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
- #define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
- #define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
- #define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
+ #define SPEAR1340_PLL1_CTR (misc_base + 0x214)
+ #define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
+ #define SPEAR1340_PLL2_CTR (misc_base + 0x220)
+ #define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
+ #define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
+ #define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
+ #define SPEAR1340_PLL4_CTR (misc_base + 0x238)
+ #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
+ #define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244)
/* PERIP_CLK_CFG bit values */
#define SPEAR1340_SPDIF_CLK_MASK 1
#define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
#define SPEAR1340_C3_CLK_MASK 1
#define SPEAR1340_C3_CLK_SHIFT 1
- #define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
+ #define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248)
#define SPEAR1340_GMAC_PHY_CLK_MASK 1
#define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
#define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
#define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
- #define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
+ #define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C)
/* I2S_CLK_CFG register mask */
#define SPEAR1340_I2S_SCLK_X_MASK 0x1F
#define SPEAR1340_I2S_SCLK_X_SHIFT 27
#define SPEAR1340_I2S_SRC_CLK_MASK 2
#define SPEAR1340_I2S_SRC_CLK_SHIFT 0
- #define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
- #define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
- #define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
- #define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
- #define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
- #define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
- #define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
- #define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
- #define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
- #define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
- #define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
- #define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
- #define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
- #define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
- #define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
+ #define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250)
+ #define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254)
+ #define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258)
+ #define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C)
+ #define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260)
+ #define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264)
+ #define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270)
+ #define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274)
+ #define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C)
+ #define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284)
+ #define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C)
+ #define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294)
+ #define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C)
+ #define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304)
+ #define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C)
#define SPEAR1340_RTC_CLK_ENB 31
#define SPEAR1340_ADC_CLK_ENB 30
#define SPEAR1340_C3_CLK_ENB 29
#define SPEAR1340_SYSROM_CLK_ENB 1
#define SPEAR1340_BUS_CLK_ENB 0
- #define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
+ #define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310)
#define SPEAR1340_THSENS_CLK_ENB 8
#define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
#define SPEAR1340_ACP_CLK_ENB 6
#define SPEAR1340_DDR_CORE_CLK_ENB 1
#define SPEAR1340_DDR_CTRL_CLK_ENB 0
- #define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
+ #define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314)
#define SPEAR1340_PLGPIO_CLK_ENB 18
#define SPEAR1340_VIDEO_DEC_CLK_ENB 16
#define SPEAR1340_VIDEO_ENC_CLK_ENB 15
static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
"pll2_clk", };
- void __init spear1340_clk_init(void)
+ void __init spear1340_clk_init(void __iomem *misc_base)
{
struct clk *clk, *clk1;
SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
- clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0,
+ clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "acp_clk");
- clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0,
+ clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "e2800000.gpio");
- clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0,
+ clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "video_dec");
- clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0,
+ clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
0, &_lock);
clk_register_clkdev(clk, NULL, "video_enc");
- clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0,
+ clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "spear_vip");
- clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0,
+ clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "d0200000.cam0");
- clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0,
+ clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "d0300000.cam1");
- clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0,
+ clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "d0400000.cam2");
- clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0,
+ clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
&_lock);
clk_register_clkdev(clk, NULL, "d0500000.cam3");
#include <linux/clk-provider.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/platform_data/clk-ux500.h>
- #include <mach/db8500-regs.h>
#include "clk.h"
- void u8500_clk_init(void)
+ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+ u32 clkrst5_base, u32 clkrst6_base)
{
struct prcmu_fw_version *fw_version;
const char *sgaclk_parent = NULL;
*/
/* PRCC P-clocks */
- clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
BIT(0), 0);
clk_register_clkdev(clk, "apb_pclk", "uart0");
- clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
BIT(1), 0);
clk_register_clkdev(clk, "apb_pclk", "uart1");
- clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
BIT(2), 0);
clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
- clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
BIT(3), 0);
clk_register_clkdev(clk, "apb_pclk", "msp0");
clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
- clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
BIT(4), 0);
clk_register_clkdev(clk, "apb_pclk", "msp1");
clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
- clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
BIT(5), 0);
clk_register_clkdev(clk, "apb_pclk", "sdi0");
- clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
BIT(6), 0);
clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
- clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
BIT(7), 0);
clk_register_clkdev(clk, NULL, "spi3");
- clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
BIT(8), 0);
clk_register_clkdev(clk, "apb_pclk", "slimbus0");
- clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
BIT(9), 0);
clk_register_clkdev(clk, NULL, "gpio.0");
clk_register_clkdev(clk, NULL, "gpio.1");
clk_register_clkdev(clk, NULL, "gpioblock0");
- clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
BIT(10), 0);
clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
- clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
+ clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
BIT(11), 0);
clk_register_clkdev(clk, "apb_pclk", "msp3");
clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
- clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
BIT(0), 0);
clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
- clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
BIT(1), 0);
clk_register_clkdev(clk, NULL, "spi2");
- clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
BIT(2), 0);
clk_register_clkdev(clk, NULL, "spi1");
- clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
BIT(3), 0);
clk_register_clkdev(clk, NULL, "pwl");
- clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
BIT(4), 0);
clk_register_clkdev(clk, "apb_pclk", "sdi4");
- clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
BIT(5), 0);
clk_register_clkdev(clk, "apb_pclk", "msp2");
clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
- clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
BIT(6), 0);
clk_register_clkdev(clk, "apb_pclk", "sdi1");
- clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
BIT(7), 0);
clk_register_clkdev(clk, "apb_pclk", "sdi3");
- clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
BIT(8), 0);
clk_register_clkdev(clk, NULL, "spi0");
- clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
BIT(9), 0);
clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
- clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
BIT(10), 0);
clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
- clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
BIT(11), 0);
clk_register_clkdev(clk, NULL, "gpio.6");
clk_register_clkdev(clk, NULL, "gpio.7");
clk_register_clkdev(clk, NULL, "gpioblock1");
- clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
+ clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
BIT(12), 0);
- clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
BIT(0), 0);
- clk_register_clkdev(clk, NULL, "fsmc");
+ clk_register_clkdev(clk, "fsmc", NULL);
+ clk_register_clkdev(clk, NULL, "smsc911x");
- clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
BIT(1), 0);
clk_register_clkdev(clk, "apb_pclk", "ssp0");
- clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
BIT(2), 0);
clk_register_clkdev(clk, "apb_pclk", "ssp1");
- clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
BIT(3), 0);
clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
- clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
BIT(4), 0);
clk_register_clkdev(clk, "apb_pclk", "sdi2");
- clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
BIT(5), 0);
clk_register_clkdev(clk, "apb_pclk", "ske");
clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
- clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
BIT(6), 0);
clk_register_clkdev(clk, "apb_pclk", "uart2");
- clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
BIT(7), 0);
clk_register_clkdev(clk, "apb_pclk", "sdi5");
- clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
+ clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
BIT(8), 0);
clk_register_clkdev(clk, NULL, "gpio.2");
clk_register_clkdev(clk, NULL, "gpio.3");
clk_register_clkdev(clk, NULL, "gpio.5");
clk_register_clkdev(clk, NULL, "gpioblock2");
- clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
+ clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
BIT(0), 0);
clk_register_clkdev(clk, "usb", "musb-ux500.0");
- clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
+ clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
BIT(1), 0);
clk_register_clkdev(clk, NULL, "gpio.8");
clk_register_clkdev(clk, NULL, "gpioblock3");
- clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
BIT(0), 0);
clk_register_clkdev(clk, "apb_pclk", "rng");
- clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
BIT(1), 0);
clk_register_clkdev(clk, NULL, "cryp0");
clk_register_clkdev(clk, NULL, "cryp1");
- clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
BIT(2), 0);
clk_register_clkdev(clk, NULL, "hash0");
- clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
BIT(3), 0);
clk_register_clkdev(clk, NULL, "pka");
- clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
BIT(4), 0);
clk_register_clkdev(clk, NULL, "hash1");
- clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
BIT(5), 0);
clk_register_clkdev(clk, NULL, "cfgreg");
- clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
BIT(6), 0);
clk_register_clkdev(clk, "apb_pclk", "mtu0");
- clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
+ clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
BIT(7), 0);
clk_register_clkdev(clk, "apb_pclk", "mtu1");
/* Periph1 */
clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
- U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "uart0");
clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
- U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "uart1");
clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
- U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "nmk-i2c.1");
clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
- U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "msp0");
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
- U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "msp1");
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
- U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdi0");
clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
- U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "nmk-i2c.2");
clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
- U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "slimbus0");
clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
- U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "nmk-i2c.4");
clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
- U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
+ clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "msp3");
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
/* Periph2 */
clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
- U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
+ clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "nmk-i2c.3");
clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
- U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
+ clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdi4");
clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
- U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
+ clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "msp2");
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
- U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
+ clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdi1");
clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
- U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
+ clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdi3");
/* Note that rate is received from parent. */
clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
- U8500_CLKRST2_BASE, BIT(6),
+ clkrst2_base, BIT(6),
CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
- U8500_CLKRST2_BASE, BIT(7),
+ clkrst2_base, BIT(7),
CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
/* Periph3 */
clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
- U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
+ clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "ssp0");
clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
- U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
+ clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "ssp1");
clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
- U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
+ clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "nmk-i2c.0");
clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
- U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
+ clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdi2");
clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
- U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
+ clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "ske");
clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
- U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
+ clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "uart2");
clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
- U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
+ clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdi5");
/* Periph6 */
clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
- U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
+ clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "rng");
}
obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
+ obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
-obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
+ obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
+obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
+obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
#include <crypto/scatterwalk.h>
#include <linux/platform_data/crypto-ux500.h>
- #include <mach/hardware.h>
#include "cryp_p.h"
#include "cryp.h"
.shutdown = ux500_cryp_shutdown,
.driver = {
.owner = THIS_MODULE,
- .name = "cryp1"
+ .name = "cryp1",
.pm = &ux500_cryp_pm,
}
};
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
-obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
obj-$(CONFIG_ARM_GIC) += irq-gic.o
obj-$(CONFIG_ARM_VIC) += irq-vic.o
+ obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
-#include <asm/mach/irq.h>
#define DRIVER_NAME "pinmux-sirf"
kfree(map);
}
-static struct pinctrl_ops sirfsoc_pctrl_ops = {
+static const struct pinctrl_ops sirfsoc_pctrl_ops = {
.get_groups_count = sirfsoc_get_groups_count,
.get_group_name = sirfsoc_get_group_name,
.get_group_pins = sirfsoc_get_group_pins,
return 0;
}
-static struct pinmux_ops sirfsoc_pinmux_ops = {
+static const struct pinmux_ops sirfsoc_pinmux_ops = {
.enable = sirfsoc_pinmux_enable,
.disable = sirfsoc_pinmux_disable,
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
struct sirfsoc_gpio_bank, chip);
- return irq_find_mapping(bank->domain, offset);
+ return irq_create_mapping(bank->domain, offset);
}
static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
u32 status, ctrl;
int idx = 0;
- unsigned int first_irq;
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
return;
}
- first_irq = bank->domain->revmap_data.legacy.first_irq;
-
while (status) {
ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
pr_debug("%s: gpio id %d idx %d happens\n",
__func__, bank->id, idx);
- generic_handle_irq(first_irq + idx);
+ generic_handle_irq(irq_find_mapping(bank->domain, idx));
}
idx++;
const unsigned long *p = (const unsigned long *)pullups;
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- n = find_first_bit(p + i, BITS_PER_LONG);
- while (n < BITS_PER_LONG) {
+ for_each_set_bit(n, p + i, BITS_PER_LONG) {
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
u32 val = readl(sgpio_bank[i].chip.regs + offset);
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
writel(val, sgpio_bank[i].chip.regs + offset);
-
- n = find_next_bit(p + i, BITS_PER_LONG, n + 1);
}
}
}
const unsigned long *p = (const unsigned long *)pulldowns;
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- n = find_first_bit(p + i, BITS_PER_LONG);
- while (n < BITS_PER_LONG) {
+ for_each_set_bit(n, p + i, BITS_PER_LONG) {
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
u32 val = readl(sgpio_bank[i].chip.regs + offset);
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
writel(val, sgpio_bank[i].chip.regs + offset);
-
- n = find_next_bit(p + i, BITS_PER_LONG, n + 1);
}
}
}
goto out;
}
- bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
- SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
- &sirfsoc_gpio_irq_simple_ops, bank);
+ bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
+ &sirfsoc_gpio_irq_simple_ops, bank);
if (!bank->domain) {
pr_err("%s: Failed to create irqdomain\n", np->full_name);
#include <linux/uaccess.h>
#include <linux/io.h>
- #include <mach/hardware.h>
#include <asm/irq.h>
- #include <plat/regs-rtc.h>
+ #include "rtc-s3c.h"
enum s3c_cpu_type {
TYPE_S3C2410,
static void __iomem *s3c_rtc_base;
static int s3c_rtc_alarmno = NO_IRQ;
static int s3c_rtc_tickno = NO_IRQ;
-static bool wake_en;
static enum s3c_cpu_type s3c_rtc_cpu_type;
static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
static int s3c_rtc_remove(struct platform_device *dev)
{
- struct rtc_device *rtc = platform_get_drvdata(dev);
-
platform_set_drvdata(dev, NULL);
- rtc_device_unregister(rtc);
s3c_rtc_setaie(&dev->dev, 0);
+ clk_unprepare(rtc_clk);
rtc_clk = NULL;
return 0;
return ret;
}
- clk_enable(rtc_clk);
+ clk_prepare_enable(rtc_clk);
/* check to see if everything is setup correctly */
/* register RTC and exit */
- rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
+ rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
THIS_MODULE);
if (IS_ERR(rtc)) {
err_alarm_irq:
platform_set_drvdata(pdev, NULL);
- rtc_device_unregister(rtc);
err_nortc:
s3c_rtc_enable(pdev, 0);
- clk_disable(rtc_clk);
+ clk_disable_unprepare(rtc_clk);
return ret;
}
-#ifdef CONFIG_PM
-
+#ifdef CONFIG_PM_SLEEP
/* RTC Power management control */
static int ticnt_save, ticnt_en_save;
+static bool wake_en;
-static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+static int s3c_rtc_suspend(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
+
clk_enable(rtc_clk);
/* save TICNT for anyone using periodic interrupts */
ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
}
s3c_rtc_enable(pdev, 0);
- if (device_may_wakeup(&pdev->dev) && !wake_en) {
+ if (device_may_wakeup(dev) && !wake_en) {
if (enable_irq_wake(s3c_rtc_alarmno) == 0)
wake_en = true;
else
- dev_err(&pdev->dev, "enable_irq_wake failed\n");
+ dev_err(dev, "enable_irq_wake failed\n");
}
clk_disable(rtc_clk);
return 0;
}
-static int s3c_rtc_resume(struct platform_device *pdev)
+static int s3c_rtc_resume(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
unsigned int tmp;
clk_enable(rtc_clk);
writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
}
- if (device_may_wakeup(&pdev->dev) && wake_en) {
+ if (device_may_wakeup(dev) && wake_en) {
disable_irq_wake(s3c_rtc_alarmno);
wake_en = false;
}
return 0;
}
-#else
-#define s3c_rtc_suspend NULL
-#define s3c_rtc_resume NULL
#endif
+static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
+
#ifdef CONFIG_OF
static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
[TYPE_S3C2410] = { TYPE_S3C2410 },
static struct platform_driver s3c_rtc_driver = {
.probe = s3c_rtc_probe,
.remove = s3c_rtc_remove,
- .suspend = s3c_rtc_suspend,
- .resume = s3c_rtc_resume,
.id_table = s3c_rtc_driver_ids,
.driver = {
.name = "s3c-rtc",
.owner = THIS_MODULE,
+ .pm = &s3c_rtc_pm_ops,
.of_match_table = of_match_ptr(s3c_rtc_dt_match),
},
};
*
* This function calls to configures the rmi4 touchpad device
*/
-int synaptics_rmi4_touchpad_config(struct synaptics_rmi4_data *pdata,
+static int synaptics_rmi4_touchpad_config(struct synaptics_rmi4_data *pdata,
struct synaptics_rmi4_fn *rfi)
{
/*
return 0;
}
+ /*
+ * Descriptor structure.
+ * Describes the number of i2c devices on the bus that speak RMI.
+ */
+ static struct synaptics_rmi4_platform_data synaptics_rmi4_platformdata = {
+ .irq_type = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
+ .x_flip = false,
+ .y_flip = true,
+ };
+
/**
* synaptics_rmi4_probe() - Initialze the i2c-client touchscreen driver
* @i2c: i2c client structure pointer
return -EIO;
}
- if (!platformdata) {
- dev_err(&client->dev, "%s: no platform data\n", __func__);
- return -EINVAL;
- }
+ if (!platformdata)
+ platformdata = &synaptics_rmi4_platformdata;
/* Allocate and initialize the instance data for this client */
rmi4_data = kcalloc(2, sizeof(struct synaptics_rmi4_data),
synaptics_rmi4_i2c_block_read(rmi4_data,
rmi4_data->fn01_data_base_addr + 1, intr_status,
rmi4_data->number_of_interrupt_register);
- retval = request_threaded_irq(platformdata->irq_number, NULL,
+ retval = request_threaded_irq(client->irq, NULL,
synaptics_rmi4_irq,
platformdata->irq_type,
DRIVER_NAME, rmi4_data);
if (retval) {
dev_err(&client->dev, "%s:Unable to get attn irq %d\n",
- __func__, platformdata->irq_number);
+ __func__, client->irq);
goto err_query_dev;
}
return retval;
err_free_irq:
- free_irq(platformdata->irq_number, rmi4_data);
+ free_irq(client->irq, rmi4_data);
err_query_dev:
regulator_disable(rmi4_data->regulator);
err_regulator_enable:
static int synaptics_rmi4_remove(struct i2c_client *client)
{
struct synaptics_rmi4_data *rmi4_data = i2c_get_clientdata(client);
- const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
rmi4_data->touch_stopped = true;
wake_up(&rmi4_data->wait);
- free_irq(pdata->irq_number, rmi4_data);
+ free_irq(client->irq, rmi4_data);
input_unregister_device(rmi4_data->input_dev);
regulator_disable(rmi4_data->regulator);
regulator_put(rmi4_data->regulator);
int retval;
unsigned char intr_status;
struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
- const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
rmi4_data->touch_stopped = true;
- disable_irq(pdata->irq_number);
+ disable_irq(rmi4_data->i2c_client->irq);
retval = synaptics_rmi4_i2c_block_read(rmi4_data,
rmi4_data->fn01_data_base_addr + 1,
int retval;
unsigned char intr_status;
struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
- const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
regulator_enable(rmi4_data->regulator);
- enable_irq(pdata->irq_number);
+ enable_irq(rmi4_data->i2c_client->irq);
rmi4_data->touch_stopped = false;
retval = synaptics_rmi4_i2c_block_read(rmi4_data,
projects / profile / ivi / kernel-x86-ivi.git / commitdiff