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fsl-ddr: Add extra cycle to turnaround times
author
Dave Liu
<daveliu@freescale.com>
Tue, 8 Dec 2009 03:56:48 +0000
(11:56 +0800)
committer
Kumar Gala
<galak@kernel.crashing.org>
Tue, 27 Apr 2010 03:37:53 +0000
(22:37 -0500)
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
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diff --git
a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index
03f9c43
..
4a282bc
100644
(file)
--- a/
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@
-198,6
+198,8
@@
static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
+ /* set the turnaround time */
+ trwt_mclk = 1;
#else /* CONFIG_FSL_DDR2 */
/*
* (tXARD and tXARDS). Empirical?