} // AddedComplexity = 400
} // HasP8Vector
-let Predicates = [HasDirectMove, HasVSX] in {
+let Predicates = [HasDirectMove] in {
// VSX direct move instructions
def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
"mfvsrd $rA, $XT", IIC_VecGeneral,
def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
"mtvsrwz $XT, $rA", IIC_VecGeneral,
[(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
-} // HasDirectMove, HasVSX
+} // HasDirectMove
+
+let Predicates = [IsISA3_0, HasDirectMove] in {
+ def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
+ "mtvsrws $XT, $rA", IIC_VecGeneral,
+ []>;
+
+ def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
+ "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
+ []>, Requires<[In64BitMode]>;
+
+ def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
+ "mfvsrld $rA, $XT", IIC_VecGeneral,
+ []>, Requires<[In64BitMode]>;
+
+} // IsISA3_0, HasDirectMove
/* Direct moves of various widths from GPR's into VSR's. Each move lines
the value up into element 0 (both BE and LE). Namely, entities smaller than
# CHECK-BE: stxvll 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x5b]
# CHECK-LE: stxvll 57, 12, 27 # encoding: [0x5b,0xdb,0x2c,0x7f]
stxvll 57, 12, 27
+
+# P9 Direct Move Instructions
+# CHECK-BE: mtvsrws 34, 3 # encoding: [0x7c,0x43,0x03,0x27]
+# CHECK-LE: mtvsrws 34, 3 # encoding: [0x27,0x03,0x43,0x7c]
+ mtvsrws 34, 3
+
+# CHECK-BE: mtvsrdd 34, 3, 12 # encoding: [0x7c,0x43,0x63,0x67]
+# CHECK-LE: mtvsrdd 34, 3, 12 # encoding: [0x67,0x63,0x43,0x7c]
+ mtvsrdd 34, 3, 12
+
+# CHECK-BE: mfvsrld 3, 34 # encoding: [0x7c,0x43,0x02,0x67]
+# CHECK-LE: mfvsrld 3, 34 # encoding: [0x67,0x02,0x43,0x7c]
+ mfvsrld 3, 34