net/mlx5e: SHAMPO, reduce TIR indication
authorBen Ben-Ishay <benishay@nvidia.com>
Wed, 2 Mar 2022 15:07:08 +0000 (17:07 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 9 Mar 2022 19:39:35 +0000 (11:39 -0800)
SHAMPO is an RQ / WQ feature, an indication was added to the TIR in the
first place to enforce suitability between connected TIR and RQ, this
enforcement does not exist in current the Firmware implementation and was
redundant in the first place.

Fixes: 83439f3c37aa ("net/mlx5e: Add HW-GRO offload")
Signed-off-by: Ben Ben-Ishay <benishay@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en/tir.c
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
include/linux/mlx5/mlx5_ifc.h

index da169b816665050aa4b88f53ff25f819a8c51bc1..d4239e3b3c88efcc2ed0b5f0d84eb82285032b20 100644 (file)
@@ -88,9 +88,6 @@ void mlx5e_tir_builder_build_packet_merge(struct mlx5e_tir_builder *builder,
                         (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - rough_max_l2_l3_hdr_sz) >> 8);
                MLX5_SET(tirc, tirc, lro_timeout_period_usecs, pkt_merge_param->timeout);
                break;
-       case MLX5E_PACKET_MERGE_SHAMPO:
-               MLX5_SET(tirc, tirc, packet_merge_mask, MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO);
-               break;
        default:
                break;
        }
index bf80fb6124499fc4e6a0310ab92c91159b4ccbbb..3667f5ef5990f5254c90d4d8f01e03befcd5bf38 100644 (file)
@@ -3616,8 +3616,7 @@ static int set_feature_hw_gro(struct net_device *netdev, bool enable)
                goto out;
        }
 
-       err = mlx5e_safe_switch_params(priv, &new_params,
-                                      mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
+       err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
 out:
        mutex_unlock(&priv->state_lock);
        return err;
index 5743f5b3414bf674922ba1b6f9d7387536649e26..49a48d7709ac18f4846b4b236ae9731098131d28 100644 (file)
@@ -3434,7 +3434,6 @@ enum {
 enum {
        MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
        MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
-       MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO    = BIT(2),
 };
 
 enum {