clk: bcm2835: divider value has to be 1 or more

Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index a39f8a7..1fee1fd 100644 (file)
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1190,8 +1190,9 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
                div += unused_frac_mask + 1;
        div &= ~unused_frac_mask;
 
-       /* Clamp to the limits. */
-       div = max(div, unused_frac_mask + 1);
+       /* clamp to min divider of 1 */
+       div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
+       /* clamp to the highest possible fractional divider */
        div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
                                      CM_DIV_FRAC_BITS - data->frac_bits));