drm/amdkfd: Delete useless SDMA register setting on non HWS path

HW folks have confirm that we should not touch RESUME_CTX of
SDMA*_GFX_CONTEXT_CNTL when manipulating RLC queues.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index c9f04e9..0fcf7b4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -101,38 +101,12 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
        return retval;
 }
 
-static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
-               u32 instance, u32 offset)
-{
-       switch (instance) {
-       case 0:
-               return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
-       case 1:
-               return (adev->reg_offset[SDMA1_HWIP][0][1] + offset);
-       case 2:
-               return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
-       case 3:
-               return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
-       case 4:
-               return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
-       case 5:
-               return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
-       case 6:
-               return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
-       case 7:
-               return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
-       default:
-               break;
-       }
-       return 0;
-}
-
 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                             uint32_t __user *wptr, struct mm_struct *mm)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
+       uint32_t sdma_base_addr;
        unsigned long end_jiffies;
        uint32_t data;
        uint64_t data64;
@@ -141,8 +115,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
        m = get_sdma_mqd(mqd);
        sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
-       sdmax_gfx_context_cntl = sdma_v4_0_get_reg_offset(adev,
-                       m->sdma_engine_id, mmSDMA0_GFX_CONTEXT_CNTL);
 
        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
                m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
@@ -158,10 +130,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                }
                usleep_range(500, 1000);
        }
-       data = RREG32(sdmax_gfx_context_cntl);
-       data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
-                            RESUME_CTX, 0);
-       WREG32(sdmax_gfx_context_cntl, data);
 
        WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
               m->sdmax_rlcx_doorbell_offset);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 7beb1ee..7c21f06 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -489,7 +489,7 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v10_sdma_mqd *m;
-       uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
+       uint32_t sdma_base_addr;
        unsigned long end_jiffies;
        uint32_t data;
        uint64_t data64;
@@ -499,9 +499,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
        sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
        pr_debug("sdma load base addr %x for engine %d, queue %d\n", sdma_base_addr, m->sdma_engine_id, m->sdma_queue_id);
-       sdmax_gfx_context_cntl = m->sdma_engine_id ?
-               SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
-               SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
 
        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
                m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
@@ -517,10 +514,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                }
                usleep_range(500, 1000);
        }
-       data = RREG32(sdmax_gfx_context_cntl);
-       data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
-                            RESUME_CTX, 0);
-       WREG32(sdmax_gfx_context_cntl, data);
 
        WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
               m->sdmax_rlcx_doorbell_offset);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 1d2f9d8..4c4e6b7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -433,17 +433,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                }
                usleep_range(500, 1000);
        }
-       if (m->sdma_engine_id) {
-               data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
-               data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
-                               RESUME_CTX, 0);
-               WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
-       } else {
-               data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
-               data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
-                               RESUME_CTX, 0);
-               WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
-       }
 
        data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
                             ENABLE, 1);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index d9be175..4894108 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -417,17 +417,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                }
                usleep_range(500, 1000);
        }
-       if (m->sdma_engine_id) {
-               data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
-               data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
-                               RESUME_CTX, 0);
-               WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
-       } else {
-               data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
-               data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
-                               RESUME_CTX, 0);
-               WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
-       }
 
        data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
                             ENABLE, 1);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 39a6a63..acd7296 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -388,7 +388,7 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
+       uint32_t sdma_base_addr;
        unsigned long end_jiffies;
        uint32_t data;
        uint64_t data64;
@@ -397,9 +397,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
        m = get_sdma_mqd(mqd);
        sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
-       sdmax_gfx_context_cntl = m->sdma_engine_id ?
-               SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
-               SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
 
        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
                m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
@@ -415,10 +412,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                }
                usleep_range(500, 1000);
        }
-       data = RREG32(sdmax_gfx_context_cntl);
-       data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
-                            RESUME_CTX, 0);
-       WREG32(sdmax_gfx_context_cntl, data);
 
        WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
               m->sdmax_rlcx_doorbell_offset);