drm/amd/display: program display clock on cache match

[Why]
We seem to have an issue where high enough display clock
will not get set properly during S3 resume if we only
call vbios once

[How]
Expand condition of display clock programming to happen
even when cached display clock matches requested display
clock

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index f176779..684da3d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -625,7 +625,9 @@ static void dcn1_update_clocks(struct dccg *dccg,
        }
 
        /* dcn1 dppclk is tied to dispclk */
-       if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
+       /* program dispclk on = as a w/a for sleep resume clock ramping issues */
+       if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)
+                       || new_clocks->dispclk_khz == dccg->clks.dispclk_khz) {
                dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks);
                dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f5d8242..cfcc54f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1089,6 +1089,8 @@ static void dcn10_init_hw(struct dc *dc)
        }
 
        enable_power_gating_plane(dc->hwseq, true);
+
+       memset(&dc->res_pool->dccg->clks, 0, sizeof(dc->res_pool->dccg->clks));
 }
 
 static void reset_hw_ctx_wrap(