.set_rate = clk_factors_set_rate,
};
-struct clk *sunxi_factors_register(struct device_node *node,
- const struct factors_data *data,
- spinlock_t *lock,
- void __iomem *reg)
+static struct clk *__sunxi_factors_register(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock, void __iomem *reg,
+ unsigned long flags)
{
struct clk *clk;
struct clk_factors *factors;
parents, i,
mux_hw, &clk_mux_ops,
&factors->hw, &clk_factors_ops,
- gate_hw, &clk_gate_ops, 0);
+ gate_hw, &clk_gate_ops, CLK_IS_CRITICAL);
if (IS_ERR(clk))
goto err_register;
return NULL;
}
+struct clk *sunxi_factors_register(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock,
+ void __iomem *reg)
+{
+ return __sunxi_factors_register(node, data, lock, reg, 0);
+}
+
+struct clk *sunxi_factors_register_critical(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock,
+ void __iomem *reg)
+{
+ return __sunxi_factors_register(node, data, lock, reg, CLK_IS_CRITICAL);
+}
+
void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
{
struct clk_hw *hw = __clk_get_hw(clk);
const struct factors_data *data,
spinlock_t *lock,
void __iomem *reg);
+struct clk *sunxi_factors_register_critical(struct device_node *node,
+ const struct factors_data *data,
+ spinlock_t *lock,
+ void __iomem *reg);
void sunxi_factors_unregister(struct device_node *node, struct clk *clk);
*/
#include <linux/clk.h>
-#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
static void __init sun5i_a13_mbus_setup(struct device_node *node)
{
- struct clk *mbus;
void __iomem *reg;
reg = of_iomap(node, 0);
return;
}
- mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
- &sun5i_a13_mbus_lock, reg);
-
/* The MBUS clocks needs to be always enabled */
- __clk_get(mbus);
- clk_prepare_enable(mbus);
+ sunxi_factors_register_critical(node, &sun4i_a10_mod0_data,
+ &sun5i_a13_mbus_lock, reg);
}
CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
*/
#include <linux/clk.h>
-#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
mux->mask = SUN8I_MBUS_MUX_MASK;
mux->lock = &sun8i_a23_mbus_lock;
+ /* The MBUS clocks needs to be always enabled */
clk = clk_register_composite(NULL, clk_name, parents, num_parents,
&mux->hw, &clk_mux_ops,
&div->hw, &clk_divider_ops,
&gate->hw, &clk_gate_ops,
- 0);
+ CLK_IS_CRITICAL);
if (IS_ERR(clk))
goto err_free_gate;
goto err_unregister_clk;
kfree(parents); /* parents is deep copied */
- /* The MBUS clocks needs to be always enabled */
- __clk_get(clk);
- clk_prepare_enable(clk);
return;
*/
#include <linux/clk.h>
-#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
static void __init sun9i_a80_gt_setup(struct device_node *node)
{
void __iomem *reg;
- struct clk *gt;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
return;
}
- gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
- &sun9i_a80_gt_lock, reg);
-
/* The GT bus clock needs to be always enabled */
- __clk_get(gt);
- clk_prepare_enable(gt);
+ sunxi_factors_register_critical(node, &sun9i_a80_gt_data,
+ &sun9i_a80_gt_lock, reg);
}
CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
};
static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
- const struct mux_data *data)
+ const struct mux_data *data,
+ unsigned long flags)
{
struct clk *clk;
const char *clk_name = node->name;
}
clk = clk_register_mux(NULL, clk_name, parents, i,
- CLK_SET_RATE_PARENT, reg,
+ CLK_SET_RATE_PARENT | flags, reg,
data->shift, SUNXI_MUX_GATE_WIDTH,
0, &clk_lock);
static void __init sun4i_cpu_clk_setup(struct device_node *node)
{
- struct clk *clk;
-
- clk = sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data);
- if (!clk)
- return;
-
/* Protect CPU clock */
- __clk_get(clk);
- clk_prepare_enable(clk);
+ sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);
}
CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
sun4i_cpu_clk_setup);
static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
{
- sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data);
+ sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);
}
CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
sun6i_ahb1_mux_clk_setup);
static void __init sun8i_ahb2_clk_setup(struct device_node *node)
{
- sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data);
+ sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);
}
CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
sun8i_ahb2_clk_setup);
u8 shift; /* otherwise it's a normal divisor with this shift */
u8 pow; /* is it power-of-two based? */
u8 gate; /* is it independently gateable? */
+ bool critical;
} div[SUNXI_DIVS_MAX_QTY];
};
.factors = &sun4i_pll5_data,
.ndivs = 2,
.div = {
- { .shift = 0, .pow = 0, }, /* M, DDR */
+ /* Protect PLL5_DDR */
+ { .shift = 0, .pow = 0, .critical = true }, /* M, DDR */
{ .shift = 16, .pow = 1, }, /* P, other */
/* No output for the base factor clock */
}
NULL, NULL,
rate_hw, rate_ops,
gate_hw, &clk_gate_ops,
- clkflags);
+ clkflags |
+ data->div[i].critical ?
+ CLK_IS_CRITICAL : 0);
WARN_ON(IS_ERR(clk_data->clks[i]));
}
static void __init sun4i_pll5_clk_setup(struct device_node *node)
{
- struct clk **clks;
-
- clks = sunxi_divs_clk_setup(node, &pll5_divs_data);
- if (!clks)
- return;
-
- /* Protect PLL5_DDR */
- __clk_get(clks[0]);
- clk_prepare_enable(clks[0]);
+ sunxi_divs_clk_setup(node, &pll5_divs_data);
}
CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
sun4i_pll5_clk_setup);