"Disable default unroll preference.">;
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
- "SiFive 7-Series processors">;
+ "SiFive 7-Series processors",
+ [TuneNoDefaultUnroll]>;
//===----------------------------------------------------------------------===//
// Named operands for CSR instructions.
def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [],
- [TuneSiFive7, TuneNoDefaultUnroll]>;
+ [TuneSiFive7]>;
def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit],
- [TuneSiFive7, TuneNoDefaultUnroll]>;
+ [TuneSiFive7]>;
def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM,
FeatureStdExtC]>;
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtC],
- [TuneSiFive7, TuneNoDefaultUnroll]>;
+ [TuneSiFive7]>;
def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- [TuneSiFive7, TuneNoDefaultUnroll]>;
+ [TuneSiFive7]>;
def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
FeatureStdExtM,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- [TuneSiFive7, TuneNoDefaultUnroll]>;
+ [TuneSiFive7]>;
//===----------------------------------------------------------------------===//
// Define the RISC-V target.