</p>
<ul>
+<li>GL_ARB_post_depth_coverage on nvc0 (GM200+)</li>
<li>GL_ARB_shader_viewport_layer_array on nvc0 (GM200+)</li>
<li>GL_AMD_vertex_shader_layer on nvc0 (GM200+)</li>
<li>GL_AMD_vertex_shader_viewport_index on nvc0 (GM200+)</li>
unsigned numColourResults;
bool writesDepth;
bool earlyFragTests;
+ bool postDepthCoverage;
bool separateFragData;
bool usesDiscard;
bool persampleInvocation;
case TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL:
info->prop.fp.earlyFragTests = prop->u[0].Data;
break;
+ case TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE:
+ info->prop.fp.postDepthCoverage = prop->u[0].Data;
+ break;
case TGSI_PROPERTY_MUL_ZERO_WINS:
info->io.mul_zero_wins = prop->u[0].Data;
break;
#define NVC0_3D_UNK0F00__ESIZE 0x00000004
#define NVC0_3D_UNK0F00__LEN 0x00000004
+#define NVC0_3D_POST_DEPTH_COVERAGE 0x00000f1c
+
#define NVE4_3D_UNK0F20(i0) (0x00000f20 + 0x4*(i0))
#define NVE4_3D_UNK0F20__ESIZE 0x00000004
#define NVE4_3D_UNK0F20__LEN 0x00000005
fp->fp.early_z = info->prop.fp.earlyFragTests;
fp->fp.sample_mask_in = info->prop.fp.usesSampleMaskIn;
fp->fp.reads_framebuffer = info->prop.fp.readsFramebuffer;
+ fp->fp.post_depth_coverage = info->prop.fp.postDepthCoverage;
/* Mark position xy and layer as read */
if (fp->fp.reads_framebuffer)
bool force_persample_interp;
bool flatshade;
bool reads_framebuffer;
+ bool post_depth_coverage;
} fp;
struct {
uint32_t tess_mode; /* ~0 if defined by the other stage */
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
+ case PIPE_CAP_POST_DEPTH_COVERAGE:
return class_3d >= GM200_3D_CLASS;
case PIPE_CAP_TGSI_BALLOT:
return class_3d >= NVE4_3D_CLASS;
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
- case PIPE_CAP_POST_DEPTH_COVERAGE:
return 0;
case PIPE_CAP_VENDOR_ID:
uint32_t uniform_buffer_bound[6];
struct nvc0_transform_feedback_state *tfb;
bool seamless_cube_map;
+ bool post_depth_coverage;
};
struct nvc0_screen {
nvc0->state.early_z_forced = fp->fp.early_z;
IMMED_NVC0(push, NVC0_3D(FORCE_EARLY_FRAGMENT_TESTS), fp->fp.early_z);
}
+ if (fp->fp.post_depth_coverage != nvc0->state.post_depth_coverage) {
+ nvc0->state.post_depth_coverage = fp->fp.post_depth_coverage;
+ IMMED_NVC0(push, NVC0_3D(POST_DEPTH_COVERAGE),
+ fp->fp.post_depth_coverage);
+ }
BEGIN_NVC0(push, NVC0_3D(SP_SELECT(5)), 2);
PUSH_DATA (push, 0x51);