rtw89: correct CCA control
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 6 May 2022 12:02:14 +0000 (20:02 +0800)
committerKalle Valo <kvalo@kernel.org>
Wed, 11 May 2022 05:31:02 +0000 (08:31 +0300)
EDCCA signal can block transmitting in certain situation, so ignore this
signal and use others to decide transmitting time.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220506120216.58567-4-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/mac.c

index e1a1699..3b61ff0 100644 (file)
@@ -1890,11 +1890,12 @@ static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
                B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA |
                B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 |
                B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 |
-               B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA);
+               B_AX_CTN_CHK_CCA_P20);
        val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
                 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 |
                 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 |
-                B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV);
+                B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV |
+                B_AX_SIFS_CHK_EDCCA);
 
        rtw89_write32(rtwdev, reg, val);