drm/amd/display: log additional register state for debug

[Why & How]
Extend existing state collection functions to add some additional
registers useful for debug, and add state collection function for DC
hubbub

Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 8d7e92d..32fb22d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -121,6 +121,10 @@ struct dcn_hubbub_registers {
        uint32_t DCN_VM_AGP_BASE;
        uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
        uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
+       uint32_t DCN_VM_FAULT_ADDR_MSB;
+       uint32_t DCN_VM_FAULT_ADDR_LSB;
+       uint32_t DCN_VM_FAULT_CNTL;
+       uint32_t DCN_VM_FAULT_STATUS;
        uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
        uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
        uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
@@ -233,7 +237,19 @@ struct dcn_hubbub_registers {
                type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
                type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
                type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
-               type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+               type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
+               type DCN_VM_FAULT_ADDR_MSB;\
+               type DCN_VM_FAULT_ADDR_LSB;\
+               type DCN_VM_ERROR_STATUS_CLEAR;\
+               type DCN_VM_ERROR_STATUS_MODE;\
+               type DCN_VM_ERROR_INTERRUPT_ENABLE;\
+               type DCN_VM_RANGE_FAULT_DISABLE;\
+               type DCN_VM_PRQ_FAULT_DISABLE;\
+               type DCN_VM_ERROR_STATUS;\
+               type DCN_VM_ERROR_VMID;\
+               type DCN_VM_ERROR_TABLE_LEVEL;\
+               type DCN_VM_ERROR_PIPE;\
+               type DCN_VM_ERROR_INTERRUPT_STATUS
 
 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
                type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 04303fe..ea185c8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -871,6 +871,8 @@ void hubp1_read_state_common(struct hubp *hubp)
        struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
        struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
        struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
+       uint32_t aperture_low_msb, aperture_low_lsb;
+       uint32_t aperture_high_msb, aperture_high_lsb;
 
        /* Requester */
        REG_GET(HUBPRET_CONTROL,
@@ -881,6 +883,22 @@ void hubp1_read_state_common(struct hubp *hubp)
                        MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
                        CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
 
+       REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB,
+                       MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb);
+
+       REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB,
+                       MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb);
+
+       REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB,
+                       MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb);
+
+       REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB,
+                       MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb);
+
+       // On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format
+       rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6);
+       rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6);
+
        /* DLG - Per hubp */
        REG_GET_2(BLANK_OFFSET_0,
                REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
@@ -1037,6 +1055,17 @@ void hubp1_read_state_common(struct hubp *hubp)
                        QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
                        QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
 
+       REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
+                       PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
+
+       REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+                       PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
+
+       REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+                       PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
+
+       REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+                       PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
 }
 
 void hubp1_read_state(struct hubp *hubp)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index e2f2f69..9cb8c38 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -682,6 +682,10 @@ struct dcn_hubp_state {
        uint32_t min_ttu_vblank;
        uint32_t qos_level_low_wm;
        uint32_t qos_level_high_wm;
+       uint32_t primary_surface_addr_lo;
+       uint32_t primary_surface_addr_hi;
+       uint32_t primary_meta_addr_lo;
+       uint32_t primary_meta_addr_hi;
 };
 
 struct dcn10_hubp {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 3696faf..37848f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -1388,6 +1388,12 @@ void optc1_read_otg_state(struct optc *optc1,
 
        REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
                        OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
+                       OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
+                       OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
 }
 
 bool optc1_get_otg_active_size(struct timing_generator *optc,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 29d6fbe..c50c299 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -578,6 +578,8 @@ struct dcn_otg_state {
        uint32_t underflow_occurred_status;
        uint32_t otg_enabled;
        uint32_t blank_enabled;
+       uint32_t vertical_interrupt2_en;
+       uint32_t vertical_interrupt2_line;
 };
 
 void optc1_read_otg_state(struct optc *optc1,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index 91a9305..aacb1fb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -605,6 +605,26 @@ static bool hubbub2_program_watermarks(
        return wm_pending;
 }
 
+void hubbub2_read_state(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state)
+{
+       struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+
+       if (REG(DCN_VM_FAULT_ADDR_MSB))
+               hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_MSB);
+
+       if (REG(DCN_VM_FAULT_ADDR_LSB))
+               hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_LSB);
+
+       if (REG(DCN_VM_FAULT_CNTL))
+               REG_GET(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, &hubbub_state->vm_error_mode);
+
+       if (REG(DCN_VM_FAULT_STATUS)) {
+                REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, &hubbub_state->vm_error_status);
+                REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, &hubbub_state->vm_error_vmid);
+                REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, &hubbub_state->vm_error_pipe);
+       }
+}
+
 static const struct hubbub_funcs hubbub2_funcs = {
        .update_dchub = hubbub2_update_dchub,
        .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx,
@@ -617,6 +637,7 @@ static const struct hubbub_funcs hubbub2_funcs = {
        .program_watermarks = hubbub2_program_watermarks,
        .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
        .allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+       .hubbub_read_state = hubbub2_read_state,
 };
 
 void hubbub2_construct(struct dcn20_hubbub *hubbub,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index 10af257..2f6146b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -29,16 +29,6 @@
 #include "dcn10/dcn10_hubbub.h"
 #include "dcn20_vmid.h"
 
-#define HUBBUB_REG_LIST_DCN20_COMMON()\
-       HUBBUB_REG_LIST_DCN_COMMON(), \
-       SR(DCHUBBUB_CRC_CTRL), \
-       SR(DCN_VM_FB_LOCATION_BASE),\
-       SR(DCN_VM_FB_LOCATION_TOP),\
-       SR(DCN_VM_FB_OFFSET),\
-       SR(DCN_VM_AGP_BOT),\
-       SR(DCN_VM_AGP_TOP),\
-       SR(DCN_VM_AGP_BASE)
-
 #define TO_DCN20_HUBBUB(hubbub)\
        container_of(hubbub, struct dcn20_hubbub, base)
 
@@ -50,7 +40,11 @@
        SR(DCN_VM_FB_OFFSET),\
        SR(DCN_VM_AGP_BOT),\
        SR(DCN_VM_AGP_TOP),\
-       SR(DCN_VM_AGP_BASE)
+       SR(DCN_VM_AGP_BASE),\
+       SR(DCN_VM_FAULT_ADDR_MSB), \
+       SR(DCN_VM_FAULT_ADDR_LSB), \
+       SR(DCN_VM_FAULT_CNTL), \
+       SR(DCN_VM_FAULT_STATUS)
 
 #define HUBBUB_REG_LIST_DCN20(id)\
        HUBBUB_REG_LIST_DCN20_COMMON(), \
@@ -71,7 +65,19 @@
        HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
        HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
        HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \
-       HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh)
+       HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)
 
 struct dcn20_hubbub {
        struct hubbub base;
@@ -131,4 +137,7 @@ void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
 void hubbub2_wm_read_state(struct hubbub *hubbub,
                struct dcn_hubbub_wm *wm);
 
+void hubbub2_read_state(struct hubbub *hubbub,
+               struct dcn_hubbub_state *hubbub_state);
+
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index 7e54058..5adf42a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -1080,6 +1080,12 @@ void hubp2_read_state_common(struct hubp *hubp)
                        MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
                        CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
 
+       REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                       MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);
+
+       REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
+                       MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);
+
        /* DLG - Per hubp */
        REG_GET_2(BLANK_OFFSET_0,
                REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
@@ -1236,6 +1242,17 @@ void hubp2_read_state_common(struct hubp *hubp)
                        QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
                        QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
 
+       REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
+                       PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
+
+       REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+                       PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
+
+       REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+                       PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
+
+       REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+                       PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
 }
 
 void hubp2_read_state(struct hubp *hubp)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index 42fbb5e..36044cb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -701,6 +701,7 @@ static const struct hubbub_funcs hubbub21_funcs = {
        .program_watermarks = hubbub21_program_watermarks,
        .allow_self_refresh_control = hubbub1_allow_self_refresh_control,
        .apply_DEDCN21_147_wa = hubbub21_apply_DEDCN21_147_wa,
+       .hubbub_read_state = hubbub2_read_state,
 };
 
 void hubbub21_construct(struct dcn20_hubbub *hubbub,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
index ef3ef28..d8eb2bb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
@@ -108,7 +108,19 @@
        HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
        HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
        HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
-       HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
+       HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)
 
 void dcn21_dchvm_init(struct hubbub *hubbub);
 int hubbub21_init_dchub(struct hubbub *hubbub,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
index b0c9180..3de1bcf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
@@ -833,7 +833,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
        .dmdata_set_attributes = hubp2_dmdata_set_attributes,
        .dmdata_load = hubp2_dmdata_load,
        .dmdata_status_done = hubp2_dmdata_status_done,
-       .hubp_read_state = hubp1_read_state,
+       .hubp_read_state = hubp2_read_state,
        .hubp_clear_underflow = hubp1_clear_underflow,
        .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
        .hubp_init = hubp21_init,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
index c0980da..f4414de 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
@@ -451,6 +451,7 @@ static const struct hubbub_funcs hubbub30_funcs = {
        .force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
        .force_pstate_change_control = hubbub3_force_pstate_change_control,
        .init_watermarks = hubbub3_init_watermarks,
+       .hubbub_read_state = hubbub2_read_state,
 };
 
 void hubbub3_construct(struct dcn20_hubbub *hubbub3,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
index c0bd0fb..7b59790 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
@@ -87,7 +87,19 @@
        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
-       HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh)
+       HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)
 
 void hubbub3_construct(struct dcn20_hubbub *hubbub3,
        struct dc_context *ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
index a0b96b3..1e3bd2e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
@@ -62,6 +62,7 @@ static const struct hubbub_funcs hubbub301_funcs = {
        .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
        .force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
        .force_pstate_change_control = hubbub3_force_pstate_change_control,
+       .hubbub_read_state = hubbub2_read_state,
 };
 
 void hubbub301_construct(struct dcn20_hubbub *hubbub3,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
index bb96484..b5a7fa6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -934,7 +934,8 @@ static const struct hubbub_funcs hubbub31_funcs = {
        .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
        .program_det_size = dcn31_program_det_size,
        .program_compbuf_size = dcn31_program_compbuf_size,
-       .init_crb = dcn31_init_crb
+       .init_crb = dcn31_init_crb,
+       .hubbub_read_state = hubbub2_read_state,
 };
 
 void hubbub31_construct(struct dcn20_hubbub *hubbub31,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
index 8ec98cb..298858d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
@@ -107,7 +107,19 @@
        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \
        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \
        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \
-       HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh)
+       HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \
+       HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)
 
 
 void hubbub31_construct(struct dcn20_hubbub *hubbub3,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 64daa05..d46a273 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -536,6 +536,8 @@ struct _vcs_dpi_display_rq_regs_st {
        unsigned int mrq_expansion_mode;
        unsigned int crq_expansion_mode;
        unsigned int plane1_base_address;
+       unsigned int aperture_low_addr;   // bits [47:18]
+       unsigned int aperture_high_addr;  // bits [47:18]
 };
 
 struct _vcs_dpi_display_dlg_sys_params_st {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 0638b33..713f555 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -102,6 +102,15 @@ struct hubbub_addr_config {
        } default_addrs;
 };
 
+struct dcn_hubbub_state {
+       uint32_t vm_fault_addr_msb;
+       uint32_t vm_fault_addr_lsb;
+       uint32_t vm_error_status;
+       uint32_t vm_error_vmid;
+       uint32_t vm_error_pipe;
+       uint32_t vm_error_mode;
+};
+
 struct hubbub_funcs {
        void (*update_dchub)(
                        struct hubbub *hubbub,
@@ -149,6 +158,8 @@ struct hubbub_funcs {
 
        void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
 
+       void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state);
+
        void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
 
        void (*init_watermarks)(struct hubbub *hubbub);