%and = and i64 %shr, 1
ret i64 %and
}
+
+define i32 @sbclri_i32_10(i32 %a) nounwind {
+; RV32I-LABEL: sbclri_i32_10:
+; RV32I: # %bb.0:
+; RV32I-NEXT: andi a0, a0, -1025
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbclri_i32_10:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: andi a0, a0, -1025
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbclri_i32_10:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: andi a0, a0, -1025
+; RV32IBS-NEXT: ret
+ %and = and i32 %a, -1025
+ ret i32 %and
+}
+
+define i32 @sbclri_i32_11(i32 %a) nounwind {
+; RV32I-LABEL: sbclri_i32_11:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1048575
+; RV32I-NEXT: addi a1, a1, 2047
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbclri_i32_11:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbclri a0, a0, 11
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbclri_i32_11:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbclri a0, a0, 11
+; RV32IBS-NEXT: ret
+ %and = and i32 %a, -2049
+ ret i32 %and
+}
+
+define i32 @sbclri_i32_30(i32 %a) nounwind {
+; RV32I-LABEL: sbclri_i32_30:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 786432
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbclri_i32_30:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbclri a0, a0, 30
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbclri_i32_30:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbclri a0, a0, 30
+; RV32IBS-NEXT: ret
+ %and = and i32 %a, -1073741825
+ ret i32 %and
+}
+
+define i32 @sbclri_i32_31(i32 %a) nounwind {
+; RV32I-LABEL: sbclri_i32_31:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbclri_i32_31:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbclri a0, a0, 31
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbclri_i32_31:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbclri a0, a0, 31
+; RV32IBS-NEXT: ret
+ %and = and i32 %a, -2147483649
+ ret i32 %and
+}
+
+define i32 @sbseti_i32_10(i32 %a) nounwind {
+; RV32I-LABEL: sbseti_i32_10:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ori a0, a0, 1024
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbseti_i32_10:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: ori a0, a0, 1024
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbseti_i32_10:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: ori a0, a0, 1024
+; RV32IBS-NEXT: ret
+ %or = or i32 %a, 1024
+ ret i32 %or
+}
+
+define i32 @sbseti_i32_11(i32 %a) nounwind {
+; RV32I-LABEL: sbseti_i32_11:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1
+; RV32I-NEXT: addi a1, a1, -2048
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbseti_i32_11:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbseti a0, a0, 11
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbseti_i32_11:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbseti a0, a0, 11
+; RV32IBS-NEXT: ret
+ %or = or i32 %a, 2048
+ ret i32 %or
+}
+
+define i32 @sbseti_i32_30(i32 %a) nounwind {
+; RV32I-LABEL: sbseti_i32_30:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 262144
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbseti_i32_30:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbseti a0, a0, 30
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbseti_i32_30:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbseti a0, a0, 30
+; RV32IBS-NEXT: ret
+ %or = or i32 %a, 1073741824
+ ret i32 %or
+}
+
+define i32 @sbseti_i32_31(i32 %a) nounwind {
+; RV32I-LABEL: sbseti_i32_31:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbseti_i32_31:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbseti a0, a0, 31
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbseti_i32_31:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbseti a0, a0, 31
+; RV32IBS-NEXT: ret
+ %or = or i32 %a, 2147483648
+ ret i32 %or
+}
+
+define i32 @sbinvi_i32_10(i32 %a) nounwind {
+; RV32I-LABEL: sbinvi_i32_10:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xori a0, a0, 1024
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbinvi_i32_10:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: xori a0, a0, 1024
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbinvi_i32_10:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: xori a0, a0, 1024
+; RV32IBS-NEXT: ret
+ %xor = xor i32 %a, 1024
+ ret i32 %xor
+}
+
+define i32 @sbinvi_i32_11(i32 %a) nounwind {
+; RV32I-LABEL: sbinvi_i32_11:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 1
+; RV32I-NEXT: addi a1, a1, -2048
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbinvi_i32_11:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbinvi a0, a0, 11
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbinvi_i32_11:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbinvi a0, a0, 11
+; RV32IBS-NEXT: ret
+ %xor = xor i32 %a, 2048
+ ret i32 %xor
+}
+
+define i32 @sbinvi_i32_30(i32 %a) nounwind {
+; RV32I-LABEL: sbinvi_i32_30:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 262144
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbinvi_i32_30:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbinvi a0, a0, 30
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbinvi_i32_30:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbinvi a0, a0, 30
+; RV32IBS-NEXT: ret
+ %xor = xor i32 %a, 1073741824
+ ret i32 %xor
+}
+
+define i32 @sbinvi_i32_31(i32 %a) nounwind {
+; RV32I-LABEL: sbinvi_i32_31:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: sbinvi_i32_31:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: sbinvi a0, a0, 31
+; RV32IB-NEXT: ret
+;
+; RV32IBS-LABEL: sbinvi_i32_31:
+; RV32IBS: # %bb.0:
+; RV32IBS-NEXT: sbinvi a0, a0, 31
+; RV32IBS-NEXT: ret
+ %xor = xor i32 %a, 2147483648
+ ret i32 %xor
+}
%and = and i64 %shr, 1
ret i64 %and
}
+
+define signext i32 @sbclri_i32_10(i32 signext %a) nounwind {
+; RV64I-LABEL: sbclri_i32_10:
+; RV64I: # %bb.0:
+; RV64I-NEXT: andi a0, a0, -1025
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i32_10:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: andi a0, a0, -1025
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i32_10:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: andi a0, a0, -1025
+; RV64IBS-NEXT: ret
+ %and = and i32 %a, -1025
+ ret i32 %and
+}
+
+define signext i32 @sbclri_i32_11(i32 signext %a) nounwind {
+; RV64I-LABEL: sbclri_i32_11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2047
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i32_11:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclriw a0, a0, 11
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i32_11:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclriw a0, a0, 11
+; RV64IBS-NEXT: ret
+ %and = and i32 %a, -2049
+ ret i32 %and
+}
+
+define signext i32 @sbclri_i32_30(i32 signext %a) nounwind {
+; RV64I-LABEL: sbclri_i32_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 786432
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i32_30:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclriw a0, a0, 30
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i32_30:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclriw a0, a0, 30
+; RV64IBS-NEXT: ret
+ %and = and i32 %a, -1073741825
+ ret i32 %and
+}
+
+define signext i32 @sbclri_i32_31(i32 signext %a) nounwind {
+; RV64I-LABEL: sbclri_i32_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i32_31:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclriw a0, a0, 31
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i32_31:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclriw a0, a0, 31
+; RV64IBS-NEXT: ret
+ %and = and i32 %a, -2147483649
+ ret i32 %and
+}
+
+define i64 @sbclri_i64_10(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_10:
+; RV64I: # %bb.0:
+; RV64I-NEXT: andi a0, a0, -1025
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i64_10:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: andi a0, a0, -1025
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i64_10:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: andi a0, a0, -1025
+; RV64IBS-NEXT: ret
+ %and = and i64 %a, -1025
+ ret i64 %and
+}
+
+define i64 @sbclri_i64_11(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2047
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i64_11:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclri a0, a0, 11
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i64_11:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclri a0, a0, 11
+; RV64IBS-NEXT: ret
+ %and = and i64 %a, -2049
+ ret i64 %and
+}
+
+define i64 @sbclri_i64_30(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 786432
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i64_30:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclri a0, a0, 30
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i64_30:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclri a0, a0, 30
+; RV64IBS-NEXT: ret
+ %and = and i64 %a, -1073741825
+ ret i64 %and
+}
+
+define i64 @sbclri_i64_31(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 31
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i64_31:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclri a0, a0, 31
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i64_31:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclri a0, a0, 31
+; RV64IBS-NEXT: ret
+ %and = and i64 %a, -2147483649
+ ret i64 %and
+}
+
+define i64 @sbclri_i64_62(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_62:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 62
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i64_62:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclri a0, a0, 62
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i64_62:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclri a0, a0, 62
+; RV64IBS-NEXT: ret
+ %and = and i64 %a, -4611686018427387905
+ ret i64 %and
+}
+
+define i64 @sbclri_i64_63(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_63:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbclri_i64_63:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbclri a0, a0, 63
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbclri_i64_63:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbclri a0, a0, 63
+; RV64IBS-NEXT: ret
+ %and = and i64 %a, -9223372036854775809
+ ret i64 %and
+}
+
+define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
+; RV64I-LABEL: sbseti_i32_10:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ori a0, a0, 1024
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i32_10:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: ori a0, a0, 1024
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i32_10:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: ori a0, a0, 1024
+; RV64IBS-NEXT: ret
+ %or = or i32 %a, 1024
+ ret i32 %or
+}
+
+define signext i32 @sbseti_i32_11(i32 signext %a) nounwind {
+; RV64I-LABEL: sbseti_i32_11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2048
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i32_11:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbsetiw a0, a0, 11
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i32_11:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbsetiw a0, a0, 11
+; RV64IBS-NEXT: ret
+ %or = or i32 %a, 2048
+ ret i32 %or
+}
+
+define signext i32 @sbseti_i32_30(i32 signext %a) nounwind {
+; RV64I-LABEL: sbseti_i32_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 262144
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i32_30:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbsetiw a0, a0, 30
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i32_30:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbsetiw a0, a0, 30
+; RV64IBS-NEXT: ret
+ %or = or i32 %a, 1073741824
+ ret i32 %or
+}
+
+define signext i32 @sbseti_i32_31(i32 signext %a) nounwind {
+; RV64I-LABEL: sbseti_i32_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i32_31:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbsetiw a0, a0, 31
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i32_31:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbsetiw a0, a0, 31
+; RV64IBS-NEXT: ret
+ %or = or i32 %a, 2147483648
+ ret i32 %or
+}
+
+define i64 @sbseti_i64_10(i64 %a) nounwind {
+; RV64I-LABEL: sbseti_i64_10:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ori a0, a0, 1024
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i64_10:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: ori a0, a0, 1024
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i64_10:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: ori a0, a0, 1024
+; RV64IBS-NEXT: ret
+ %or = or i64 %a, 1024
+ ret i64 %or
+}
+
+define i64 @sbseti_i64_11(i64 %a) nounwind {
+; RV64I-LABEL: sbseti_i64_11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2048
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i64_11:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbseti a0, a0, 11
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i64_11:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbseti a0, a0, 11
+; RV64IBS-NEXT: ret
+ %or = or i64 %a, 2048
+ ret i64 %or
+}
+
+define i64 @sbseti_i64_30(i64 %a) nounwind {
+; RV64I-LABEL: sbseti_i64_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 262144
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i64_30:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbseti a0, a0, 30
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i64_30:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbseti a0, a0, 30
+; RV64IBS-NEXT: ret
+ %or = or i64 %a, 1073741824
+ ret i64 %or
+}
+
+define i64 @sbseti_i64_31(i64 %a) nounwind {
+; RV64I-LABEL: sbseti_i64_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 1
+; RV64I-NEXT: slli a1, a1, 31
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i64_31:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbseti a0, a0, 31
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i64_31:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbseti a0, a0, 31
+; RV64IBS-NEXT: ret
+ %or = or i64 %a, 2147483648
+ ret i64 %or
+}
+
+define i64 @sbseti_i64_62(i64 %a) nounwind {
+; RV64I-LABEL: sbseti_i64_62:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 1
+; RV64I-NEXT: slli a1, a1, 62
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i64_62:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbseti a0, a0, 62
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i64_62:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbseti a0, a0, 62
+; RV64IBS-NEXT: ret
+ %or = or i64 %a, 4611686018427387904
+ ret i64 %or
+}
+
+define i64 @sbseti_i64_63(i64 %a) nounwind {
+; RV64I-LABEL: sbseti_i64_63:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbseti_i64_63:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbseti a0, a0, 63
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbseti_i64_63:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbseti a0, a0, 63
+; RV64IBS-NEXT: ret
+ %or = or i64 %a, 9223372036854775808
+ ret i64 %or
+}
+
+define signext i32 @sbinvi_i32_10(i32 signext %a) nounwind {
+; RV64I-LABEL: sbinvi_i32_10:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xori a0, a0, 1024
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i32_10:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: xori a0, a0, 1024
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i32_10:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: xori a0, a0, 1024
+; RV64IBS-NEXT: ret
+ %xor = xor i32 %a, 1024
+ ret i32 %xor
+}
+
+define signext i32 @sbinvi_i32_11(i32 signext %a) nounwind {
+; RV64I-LABEL: sbinvi_i32_11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2048
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i32_11:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinviw a0, a0, 11
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i32_11:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinviw a0, a0, 11
+; RV64IBS-NEXT: ret
+ %xor = xor i32 %a, 2048
+ ret i32 %xor
+}
+
+define signext i32 @sbinvi_i32_30(i32 signext %a) nounwind {
+; RV64I-LABEL: sbinvi_i32_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 262144
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i32_30:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinviw a0, a0, 30
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i32_30:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinviw a0, a0, 30
+; RV64IBS-NEXT: ret
+ %xor = xor i32 %a, 1073741824
+ ret i32 %xor
+}
+
+define signext i32 @sbinvi_i32_31(i32 signext %a) nounwind {
+; RV64I-LABEL: sbinvi_i32_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i32_31:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinviw a0, a0, 31
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i32_31:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinviw a0, a0, 31
+; RV64IBS-NEXT: ret
+ %xor = xor i32 %a, 2147483648
+ ret i32 %xor
+}
+
+define i64 @sbinvi_i64_10(i64 %a) nounwind {
+; RV64I-LABEL: sbinvi_i64_10:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xori a0, a0, 1024
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i64_10:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: xori a0, a0, 1024
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i64_10:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: xori a0, a0, 1024
+; RV64IBS-NEXT: ret
+ %xor = xor i64 %a, 1024
+ ret i64 %xor
+}
+
+define i64 @sbinvi_i64_11(i64 %a) nounwind {
+; RV64I-LABEL: sbinvi_i64_11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -2048
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i64_11:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinvi a0, a0, 11
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i64_11:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinvi a0, a0, 11
+; RV64IBS-NEXT: ret
+ %xor = xor i64 %a, 2048
+ ret i64 %xor
+}
+
+define i64 @sbinvi_i64_30(i64 %a) nounwind {
+; RV64I-LABEL: sbinvi_i64_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 262144
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i64_30:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinvi a0, a0, 30
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i64_30:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinvi a0, a0, 30
+; RV64IBS-NEXT: ret
+ %xor = xor i64 %a, 1073741824
+ ret i64 %xor
+}
+
+define i64 @sbinvi_i64_31(i64 %a) nounwind {
+; RV64I-LABEL: sbinvi_i64_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 1
+; RV64I-NEXT: slli a1, a1, 31
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i64_31:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinvi a0, a0, 31
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i64_31:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinvi a0, a0, 31
+; RV64IBS-NEXT: ret
+ %xor = xor i64 %a, 2147483648
+ ret i64 %xor
+}
+
+define i64 @sbinvi_i64_62(i64 %a) nounwind {
+; RV64I-LABEL: sbinvi_i64_62:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 1
+; RV64I-NEXT: slli a1, a1, 62
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i64_62:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinvi a0, a0, 62
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i64_62:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinvi a0, a0, 62
+; RV64IBS-NEXT: ret
+ %xor = xor i64 %a, 4611686018427387904
+ ret i64 %xor
+}
+
+define i64 @sbinvi_i64_63(i64 %a) nounwind {
+; RV64I-LABEL: sbinvi_i64_63:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, -1
+; RV64I-NEXT: slli a1, a1, 63
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: sbinvi_i64_63:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: sbinvi a0, a0, 63
+; RV64IB-NEXT: ret
+;
+; RV64IBS-LABEL: sbinvi_i64_63:
+; RV64IBS: # %bb.0:
+; RV64IBS-NEXT: sbinvi a0, a0, 63
+; RV64IBS-NEXT: ret
+ %xor = xor i64 %a, 9223372036854775808
+ ret i64 %xor
+}