amd: replace 0x028848 with the register definition
authorMarek Olšák <marek.olsak@amd.com>
Tue, 20 Oct 2020 21:18:16 +0000 (17:18 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Sat, 24 Oct 2020 00:51:22 +0000 (20:51 -0400)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7264>

src/amd/common/ac_shadowed_regs.c
src/amd/vulkan/si_cmd_buffer.c
src/gallium/drivers/radeonsi/si_state.c

index 1ef2df5..77cab6a 100644 (file)
@@ -649,7 +649,7 @@ static const struct ac_reg_range Gfx103ContextShadowRange[] = {
    },
    {
       R_02882C_PA_SU_PRIM_FILTER_CNTL,
-      0x028848 - R_02882C_PA_SU_PRIM_FILTER_CNTL + 4,
+      R_028848_PA_CL_VRS_CNTL - R_02882C_PA_SU_PRIM_FILTER_CNTL + 4,
    },
    {
       R_028A00_PA_SU_POINT_SIZE,
index 5f77211..7be781c 100644 (file)
@@ -478,7 +478,9 @@ si_emit_graphics(struct radv_device *device,
 
                if (physical_device->rad_info.chip_class >= GFX10_3) {
                        radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
-                       radeon_set_context_reg(cs, 0x28848, 1 << 9); /* This fixes sample shading. */
+                        /* This allows sample shading. */
+                       radeon_set_context_reg(cs, R_028848_PA_CL_VRS_CNTL,
+                                               S_028848_SAMPLE_ITER_COMBINER_MODE(1));
                }
 
                if (physical_device->rad_info.chip_class == GFX10) {
index 36d05cd..0352345 100644 (file)
@@ -5358,7 +5358,9 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
 
    if (sctx->chip_class >= GFX10_3) {
       si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
-      si_pm4_set_reg(pm4, 0x28848, 1 << 9); /* This fixes sample shading. */
+      /* This allows sample shading. */
+      si_pm4_set_reg(pm4, R_028848_PA_CL_VRS_CNTL,
+                     S_028848_SAMPLE_ITER_COMBINER_MODE(1));
    }
 
    sctx->cs_preamble_state = pm4;