: Pat <(IntID I32:$Rs, I32:$Rt),
(MI I32:$Rs, I32:$Rt)>;
+class T_PP_pat <InstHexagon MI, Intrinsic IntID>
+ : Pat <(IntID I64:$Rs, I64:$Rt),
+ (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
+
class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
: Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
(MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
+/********************************************************************
+* ALU64/ALU *
+*********************************************************************/
+def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>;
+def: T_RR_pat<A2_subsat, int_hexagon_A2_subsat>;
+def: T_PP_pat<A2_addp, int_hexagon_A2_addp>;
+def: T_PP_pat<A2_subp, int_hexagon_A2_subp>;
+
+def: T_PP_pat<A2_andp, int_hexagon_A2_andp>;
+def: T_PP_pat<A2_orp, int_hexagon_A2_orp>;
+def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>;
+
+def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
+def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
+
//
// ALU 32 types.
//
--- /dev/null
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
+target triple = "hexagon"
+
+; CHECK: test13:
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}, r{{[0-9]+}}):sat
+define i32 @test13(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addsat(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+
+; CHECK: test14:
+; CHECK: r{{[0-9]+}} = sub(r{{[0-9]+}}, r{{[0-9]+}}):sat
+define i32 @test14(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subsat(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+
+; CHECK: test61:
+; CHECK: r{{[0-9]+:[0-9]+}} = packhl(r{{[0-9]+}}, r{{[0-9]+}})
+define i64 @test61(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.S2.packhl(i32 %Rs, i32 %Rt)
+ ret i64 %0
+}
+
+declare i32 @llvm.hexagon.A2.addsat(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subsat(i32, i32) #1
+declare i64 @llvm.hexagon.S2.packhl(i32, i32) #1