This is used by the old LCD implementation which is to be removed.
Drop it and LCD_OUTPUT_BPP also.
Signed-off-by: Simon Glass <sjg@chromium.org>
#include <asm/hardware.h>
-/*
- * Hardware drivers
- */
-
-/* LCD */
-#define LCD_BPP LCD_COLOR8
-
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-/*
- * Hardware drivers
- */
-
-/* LCD */
-#define LCD_BPP LCD_COLOR8
-
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-/* general purpose I/O */
-
-/* LCD */
-#define LCD_BPP LCD_COLOR8
-
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x70000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
-
-/* LCD */
-#define LCD_BPP LCD_COLOR16
-#define LCD_OUTPUT_BPP 24
-
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
-/*
- * Hardware drivers
- */
-
-/* LCD */
-#define LCD_BPP LCD_COLOR8
-
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#include <configs/bur_cfg_common.h>
#include <configs/bur_am335x_common.h>
#include <linux/stringify.h>
-/* ------------------------------------------------------------------------- */
-#define LCD_BPP LCD_COLOR32
-
-/* memory */
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xfff))
-/*
- * Hardware drivers
- */
-
-/* LCD */
-#define LCD_BPP LCD_COLOR8
-
/* SDRAM */
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xfff))
-/*
- * Hardware drivers
- */
-/* LCD */
-#define LCD_BPP LCD_COLOR8
-
/* SDRAM */
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
#endif /* __ASSEMBLY__ */
-/* LCD console */
-#define LCD_BPP LCD_COLOR16
-
#endif /* __CONFIG_H */
#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
#endif /* __ASSEMBLY__ */
-/* LCD console */
-#define LCD_BPP LCD_COLOR16
-
#endif /* __CONFIG_H */
#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33
#endif /* __ASSEMBLY__ */
-/* LCD console */
-#define LCD_BPP LCD_COLOR16
-
#endif /* __CONFIG_H */