drm/amd/display: New sequence for HUBP blank

[WHY]
DCN30 has a bug where blanking HUBP blocks pstate allow unless
HUBP_DISABLE is toggled afterwards.

[HOW]
Create a HW sequence for blanking HUBP.
1. Wait for enter VBLANK
2. Set HUBP_BLANK
3. Make sure HUBP_IN_BLANK = 1
4. Toggle HUBP_DISABLE on and off to perform soft reset

All existing calls to hubp->funcs->set_blank should be replaced with
this new sequence.
In wait_for_mpcc_disconnect, only blank the pipe being disconnected, and
leave all other pipes unmodified.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cfc130e2d6fd01241e3ef0788f03250bd45a2c61..add86d4086e8318f23fecd4dadbfa9fc8448b1f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2624,7 +2624,7 @@ static void dcn10_update_dchubp_dpp(
        hws->funcs.update_plane_addr(dc, pipe_ctx);
 
        if (is_pipe_tree_visible(pipe_ctx))
-               hubp->funcs->set_blank(hubp, false);
+               dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
 }
 
 void dcn10_blank_pixel_data(
@@ -3135,13 +3135,16 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
        return;
 }
 
-static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
+static struct pipe_ctx *get_pipe_ctx_by_hubp_inst(struct dc_state *context, int mpcc_inst)
 {
        int i;
 
-       for (i = 0; i < res_pool->pipe_count; i++) {
-               if (res_pool->hubps[i]->inst == mpcc_inst)
-                       return res_pool->hubps[i];
+       for (i = 0; i < MAX_PIPES; i++) {
+               if (context->res_ctx.pipe_ctx[i].plane_res.hubp
+                               && context->res_ctx.pipe_ctx[i].plane_res.hubp->inst == mpcc_inst) {
+                       return &context->res_ctx.pipe_ctx[i];
+               }
+
        }
        ASSERT(false);
        return NULL;
@@ -3164,11 +3167,23 @@ void dcn10_wait_for_mpcc_disconnect(
 
        for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
                if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
-                       struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
+                       struct pipe_ctx *restore_bottom_pipe;
+                       struct pipe_ctx *restore_top_pipe;
+                       struct pipe_ctx *inst_pipe_ctx = get_pipe_ctx_by_hubp_inst(dc->current_state, mpcc_inst);
 
+                       ASSERT(inst_pipe_ctx);
                        res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
                        pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
-                       hubp->funcs->set_blank(hubp, true);
+                       /*
+                        * Set top and bottom pipes NULL, as we don't want
+                        * to blank those pipes when disconnecting from MPCC
+                        */
+                       restore_bottom_pipe = inst_pipe_ctx->bottom_pipe;
+                       restore_top_pipe = inst_pipe_ctx->top_pipe;
+                       inst_pipe_ctx->top_pipe = inst_pipe_ctx->bottom_pipe = NULL;
+                       dc->hwss.set_hubp_blank(dc, inst_pipe_ctx, true);
+                       inst_pipe_ctx->top_pipe = restore_top_pipe;
+                       inst_pipe_ctx->bottom_pipe = restore_bottom_pipe;
                }
        }
 
@@ -3721,3 +3736,10 @@ void dcn10_get_clock(struct dc *dc,
                                dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
 
 }
+
+void dcn10_set_hubp_blank(const struct dc *dc,
+                               struct pipe_ctx *pipe_ctx,
+                               bool blank_enable)
+{
+       pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, blank_enable);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index dee8ad1ebaa4e3efbc5525d60b441a131ab9f4f8..89e6dfb63da0c1990ef4705aaa4f132ca7aec725 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -204,5 +204,8 @@ void dcn10_wait_for_pending_cleared(struct dc *dc,
                struct dc_state *context);
 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
 void dcn10_verify_allow_pstate_change_high(struct dc *dc);
+void dcn10_set_hubp_blank(const struct dc *dc,
+                               struct pipe_ctx *pipe_ctx,
+                               bool blank_enable);
 
 #endif /* __DC_HWSS_DCN10_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index 254300b06b434b0332df1f93e5c56a18d17fcc58..2f1b802e66a13e7afab10a6fa1ca1f104e643188 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -79,6 +79,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
        .set_backlight_level = dce110_set_backlight_level,
        .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
        .set_pipe = dce110_set_pipe,
+       .set_hubp_blank = dcn10_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn10_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6470f5c7dfeabc61522dcf667f2b5da6a9b04184..b74f79575cdf0ad049ecfba4ca06c39ccf2d0382 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1571,7 +1571,7 @@ static void dcn20_update_dchubp_dpp(
 
 
        if (is_pipe_tree_visible(pipe_ctx))
-               hubp->funcs->set_blank(hubp, false);
+               dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
 }
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index de9dcbeea150d4a395d9f33eedbe05017bb455cf..51a4166e975079caa604c2d9414d59d80a15a9fe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -94,6 +94,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
        .optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
 #endif
        .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
+       .set_hubp_blank = dcn10_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 074e2713257f179dbc8cc642665e3d50765db686..0597391b21716bd89a138a9930c6a5f5415974e7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -99,6 +99,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
 #endif
        .is_abm_supported = dcn21_is_abm_supported,
        .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
+       .set_hubp_blank = dcn10_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index b83c13d3d8b74c720870087ecea1d6ed4d7cf9e9..7f26c9444933730ea7258f4d2b43614a05011ae9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -836,6 +836,53 @@ void dcn30_hardware_release(struct dc *dc)
                                dc->res_pool->hubbub, true, true);
 }
 
+void dcn30_set_hubp_blank(const struct dc *dc,
+               struct pipe_ctx *pipe_ctx,
+               bool blank_enable)
+{
+       struct pipe_ctx *mpcc_pipe;
+       struct pipe_ctx *odm_pipe;
+
+       if (blank_enable) {
+               struct plane_resource *plane_res = &pipe_ctx->plane_res;
+               struct stream_resource *stream_res = &pipe_ctx->stream_res;
+
+               /* Wait for enter vblank */
+               stream_res->tg->funcs->wait_for_state(stream_res->tg, CRTC_STATE_VBLANK);
+
+               /* Blank HUBP to allow p-state during blank on all timings */
+               pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
+               /* Confirm hubp in blank */
+               ASSERT(plane_res->hubp->funcs->hubp_in_blank(plane_res->hubp));
+               /* Toggle HUBP_DISABLE */
+               plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, true);
+               plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, false);
+               for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) {
+                       mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
+                       /* Confirm hubp in blank */
+                       ASSERT(mpcc_pipe->plane_res.hubp->funcs->hubp_in_blank(mpcc_pipe->plane_res.hubp));
+                       /* Toggle HUBP_DISABLE */
+                       mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, true);
+                       mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, false);
+
+               }
+               for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+                       odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, true);
+                       /* Confirm hubp in blank */
+                       ASSERT(odm_pipe->plane_res.hubp->funcs->hubp_in_blank(odm_pipe->plane_res.hubp));
+                       /* Toggle HUBP_DISABLE */
+                       odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, true);
+                       odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, false);
+               }
+       } else {
+               pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
+               for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
+                       mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
+               for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+                       odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, false);
+       }
+}
+
 void dcn30_set_disp_pattern_generator(const struct dc *dc,
                struct pipe_ctx *pipe_ctx,
                enum controller_dp_test_pattern test_pattern,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index bfc97e2ece61cbd703462950bab43e5f51a4b858..1103f6356e901d15bfb4ef492537be62f116d348 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -79,4 +79,8 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
                const struct tg_color *solid_color,
                int width, int height, int offset);
 
+void dcn30_set_hubp_blank(const struct dc *dc,
+               struct pipe_ctx *pipe_ctx,
+               bool blank_enable);
+
 #endif /* __DC_HWSS_DCN30_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index c4c14e9c1309c2653bbbab16e0843f8fecd0dd24..204444fead9777cb4399fd97244380b0c7979165 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
        .hardware_release = dcn30_hardware_release,
        .set_pipe = dcn21_set_pipe,
        .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+       .set_hubp_blank = dcn30_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn30_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
index bdad72140cbcec03fe2b61a6b544ec150904d4f4..b8bf6d61005b070cf66923b01be618753dd3fce3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
        .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
        .set_pipe = dcn21_set_pipe,
        .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+       .set_hubp_blank = dcn30_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn301_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 7a19ff5d42148c9ff6703776f42f928fcdfec1ca..48378beb71c0fb19d408d1ad7a58aa2a176c6346 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -230,6 +230,10 @@ struct hw_sequencer_funcs {
                        enum dc_color_depth color_depth,
                        const struct tg_color *solid_color,
                        int width, int height, int offset);
+
+       void (*set_hubp_blank)(const struct dc *dc,
+                       struct pipe_ctx *pipe_ctx,
+                       bool blank_enable);
 };
 
 void color_space_to_black_color(