[AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA
authorJay Foad <jay.foad@amd.com>
Thu, 6 Apr 2023 16:26:05 +0000 (17:26 +0100)
committerJay Foad <jay.foad@amd.com>
Sat, 8 Apr 2023 07:39:21 +0000 (08:39 +0100)
This was causing two test failures when I applied D129208 to enable
extra verification of LiveIntervals:

  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

Differential Revision: https://reviews.llvm.org/D147721

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

index bffbf9d..710e36b 100644 (file)
@@ -294,7 +294,13 @@ bool SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {
 
       LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());
       LIS->RemoveMachineInstrFromMaps(*Sel);
+      bool ShrinkSel = Sel->getOperand(0).readsReg();
       Sel->eraseFromParent();
+      if (ShrinkSel) {
+        // The result of the V_CNDMASK was a subreg def which counted as a read
+        // from the other parts of the reg. Shrink their live ranges.
+        LIS->shrinkToUses(SelLI);
+      }
     }
   }