mtd: rawnand: fsmc: Move the ECC initialization to ->attach_chip()

The probe function is only supposed to initialize the controller
hardware but not the ECC engine. Indeed, we don't know anything about
the NAND chip(s) at this stage. Let's move the logic initializing the
ECC engine, even pretty simple, to the ->attach_chip() hook which gets
called during nand_scan() routine, after the NAND chip discovery. As
the previously mentioned logic is supposed to parse the DT for us, it
is likely that the chip->ecc.* entries be overwritten. So let's avoid
this by moving these lines to ->attach_chip().

Fixes: d7157ff49a5b ("mtd: rawnand: Use the ECC framework user input parsing bits")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 4191831df182053197bd83be636c35a116ae7070..c88421a1c078df01218fefd97bea15a8333ab1a6 100644 (file)
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -880,6 +880,20 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
        struct mtd_info *mtd = nand_to_mtd(nand);
        struct fsmc_nand_data *host = nand_to_fsmc(nand);
 
+       if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
+               nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+
+       if (!nand->ecc.size)
+               nand->ecc.size = 512;
+
+       if (AMBA_REV_BITS(host->pid) >= 8) {
+               nand->ecc.read_page = fsmc_read_page_hwecc;
+               nand->ecc.calculate = fsmc_read_hwecc_ecc4;
+               nand->ecc.correct = fsmc_bch8_correct_data;
+               nand->ecc.bytes = 13;
+               nand->ecc.strength = 8;
+       }
+
        if (AMBA_REV_BITS(host->pid) >= 8) {
                switch (mtd->oobsize) {
                case 16:
@@ -905,6 +919,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
                dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
                nand->ecc.calculate = fsmc_read_hwecc_ecc1;
                nand->ecc.correct = nand_correct_data;
+               nand->ecc.hwctl = fsmc_enable_hwecc;
                nand->ecc.bytes = 3;
                nand->ecc.strength = 1;
                nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
@@ -1055,13 +1070,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 
        mtd->dev.parent = &pdev->dev;
 
-       /*
-        * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
-        * can overwrite this value if the DT provides a different value.
-        */
-       nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-       nand->ecc.hwctl = fsmc_enable_hwecc;
-       nand->ecc.size = 512;
        nand->badblockbits = 7;
 
        if (host->mode == USE_DMA_ACCESS) {
@@ -1084,14 +1092,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
                nand->options |= NAND_KEEP_TIMINGS;
        }
 
-       if (AMBA_REV_BITS(host->pid) >= 8) {
-               nand->ecc.read_page = fsmc_read_page_hwecc;
-               nand->ecc.calculate = fsmc_read_hwecc_ecc4;
-               nand->ecc.correct = fsmc_bch8_correct_data;
-               nand->ecc.bytes = 13;
-               nand->ecc.strength = 8;
-       }
-
        nand_controller_init(&host->base);
        host->base.ops = &fsmc_nand_controller_ops;
        nand->controller = &host->base;