const MCRegisterInfo &RI, const MCInstrAnalysis *IA);
void clear() {
- VariantDescriptors.shrink_and_clear();
+ Descriptors.clear();
+ VariantDescriptors.clear();
FirstCallInst = true;
FirstReturnInst = true;
}
/// An instruction descriptor
struct InstrDesc {
- SmallVector<WriteDescriptor, 4> Writes; // Implicit writes are at the end.
+ SmallVector<WriteDescriptor, 2> Writes; // Implicit writes are at the end.
SmallVector<ReadDescriptor, 4> Reads; // Implicit reads are at the end.
// For every resource used by an instruction of this kind, this vector
// subtarget when computing the reciprocal throughput.
unsigned SchedClassID;
- bool MayLoad;
- bool MayStore;
- bool HasSideEffects;
- bool BeginGroup;
- bool EndGroup;
- bool RetireOOO;
+ unsigned MayLoad : 1;
+ unsigned MayStore : 1;
+ unsigned HasSideEffects : 1;
+ unsigned BeginGroup : 1;
+ unsigned EndGroup : 1;
+ unsigned RetireOOO : 1;
// True if all buffered resources are in-order, and there is at least one
// buffer which is a dispatch hazard (BufferSize = 0).
- bool MustIssueImmediately;
+ unsigned MustIssueImmediately : 1;
// A zero latency instruction doesn't consume any scheduler resources.
bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }
// Output dependencies.
// One entry per each implicit and explicit register definition.
- SmallVector<WriteState, 4> Defs;
+ SmallVector<WriteState, 2> Defs;
// Input dependencies.
// One entry per each implicit and explicit register use.
namespace llvm {
namespace mca {
-CodeEmitter::EncodingInfo
-CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) {
+CodeEmitter::EncodingInfo CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) {
EncodingInfo &EI = Encodings[MCID];
if (EI.second)
return EI;
auto RCU = std::make_unique<RetireControlUnit>(SM);
auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
- Opts.StoreQueueSize, Opts.AssumeNoAlias);
+ Opts.StoreQueueSize, Opts.AssumeNoAlias);
auto HWS = std::make_unique<Scheduler>(SM, *LSU);
// Create the pipeline stages.
auto Fetch = std::make_unique<EntryStage>(SrcMgr);
- auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
- *RCU, *PRF);
+ auto Dispatch =
+ std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF);
auto Execute =
std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
// An optional descriptor for this region.
llvm::StringRef Description;
// Instructions that form this region.
- llvm::SmallVector<llvm::MCInst, 8> Instructions;
+ llvm::SmallVector<llvm::MCInst, 16> Instructions;
// Source location range.
llvm::SMLoc RangeStart;
llvm::SMLoc RangeEnd;