drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing
authorNick Hoath <nicholas.hoath@intel.com>
Fri, 10 Apr 2015 12:12:25 +0000 (13:12 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 May 2015 11:03:40 +0000 (13:03 +0200)
Note that we also need this for skl.

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Note that we also need this for skl, requested by Imre.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c

index 9447b27..558d3dd 100644 (file)
@@ -6738,6 +6738,7 @@ enum skl_disp_power_wells {
 #define GEN7_HALF_SLICE_CHICKEN1_GT2   0xf100
 #define   GEN7_MAX_PS_THREAD_DEP               (8<<12)
 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE  (1<<10)
+#define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE      (1<<4)
 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
 
 #define GEN9_HALF_SLICE_CHICKEN5       0xe188
index 98424e2..b0bd9bb 100644 (file)
@@ -1050,6 +1050,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
                          STALL_DOP_GATING_DISABLE);
 
+       /* WaDisableSbeCacheDispatchPortSharing:bxt */
+       if (INTEL_REVID(dev) <= BXT_REVID_B0) {
+               WA_SET_BIT_MASKED(
+                       GEN7_HALF_SLICE_CHICKEN1,
+                       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+       }
+
        return 0;
 }