cur_cmd_header->seq);
cur_free_space -= 4;
- topaz_priv->aui32LastSync[0][cur_cmd_header->core]
- = cur_cmd_header->seq;
topaz_priv->topaz_cmd_count %= MAX_TOPAZ_CMD_COUNT;
pnw_topaz_mtx_kick(dev_priv, 0, 1);
#ifdef SYNC_FOR_EACH_COMMAND
uint32_t topaz_hw_busy;
uint32_t topaz_num_cores;
- uint32_t aui32LastSync[2][MAX_TOPAZ_CORES + 1]; //!< Last sync value sent to each core
/*Before load firmware, need to set up jitter according to resolution*/
/*The data of MTX_CMDID_SW_NEW_CODEC command contains width and length.*/
if (val & (1 << 31))
PSB_DEBUG_IRQ("TOPAZ:IRQ pin activated,cmd seq=0x%04x,"
- "sync seq: 0x%08x vs 0x%08x (MTX)\n",
- topaz_priv->aui32LastSync[0][0] ,
+ "sync seq: 0x%08x\n",
dev_priv->sequence[LNC_ENGINE_ENCODE],
*((uint32_t *)topaz_priv->topaz_mtx_wb + MTX_WRITEBACK_VALUE));
else
PSB_DEBUG_IRQ("TOPAZ:IRQ pin not activated,cmd seq=0x%04x,"
- "sync seq: 0x%08x vs 0x%08x (MTX)\n",
- topaz_priv->aui32LastSync[0][0],
+ "sync seq: 0x%08x\n",
dev_priv->sequence[LNC_ENGINE_ENCODE],
*((uint32_t *)topaz_priv->topaz_mtx_wb + MTX_WRITEBACK_VALUE));
PSB_DEBUG_GENERAL("TOPAZ: Reset MVEA successfully.\n");
- for (n = 0; n < MAX_TOPAZ_CORES + 1; n++) {
- topaz_priv->aui32LastSync[0][n] = ~0;
- topaz_priv->aui32LastSync[1][n] = ~0;
- }
-
/* create firmware storage */
for (n = 0; n < IMG_CODEC_NUM * 2; ++n) {
/* #.# malloc DRM object for fw storage */