drm/i915/dp: Fix log level for "CDS interlane align done"
authorKhaled Almahallawy <khaled.almahallawy@intel.com>
Tue, 6 Jun 2023 22:44:28 +0000 (15:44 -0700)
committerImre Deak <imre.deak@intel.com>
Wed, 7 Jun 2023 17:38:48 +0000 (20:38 +0300)
"CDS interlane align done" is a passing condition not an error.
Before adding new macros for logs it was drm_dbg_kms.

Fixes: f48eab290287 ("drm/i915/dp: Add link training debug and error printing helpers")
Cc: Imre Deak <imre.deak@intel.com>
CC: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606224428.3791006-1-khaled.almahallawy@intel.com
drivers/gpu/drm/i915/display/intel_dp_link_training.c

index 0952a70..176b610 100644 (file)
@@ -1279,7 +1279,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
                if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
                    drm_dp_128b132b_cds_interlane_align_done(link_status) &&
                    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
-                       lt_err(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
+                       lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
                        break;
                }