#include "RISCVTargetStreamer.h"
#include "RISCVBaseInfo.h"
#include "RISCVMCTargetDesc.h"
+#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/RISCVAttributes.h"
#include "llvm/Support/RISCVISAInfo.h"
OS << "\t.option\tnorelax\n";
}
+void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
+ OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
+}
+
void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
}
void emitDirectiveOptionNoRVC() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
+ void emitDirectiveVariantCC(MCSymbol &Symbol) override;
};
}
#include "MCTargetDesc/RISCVMCExpr.h"
#include "MCTargetDesc/RISCVTargetStreamer.h"
#include "RISCV.h"
+#include "RISCVMachineFunctionInfo.h"
#include "RISCVTargetMachine.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/ADT/Statistic.h"
void emitStartOfAsmFile(Module &M) override;
void emitEndOfAsmFile(Module &M) override;
+ void emitFunctionEntryLabel() override;
+
private:
void emitAttributes();
};
RTS.emitTargetAttributes(*MCSTI);
}
+void RISCVAsmPrinter::emitFunctionEntryLabel() {
+ const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>();
+ if (RMFI->isVectorCall()) {
+ auto &RTS =
+ static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
+ RTS.emitDirectiveVariantCC(*CurrentFnSym);
+ }
+ return AsmPrinter::emitFunctionEntryLabel();
+}
+
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
InVals.push_back(ArgValue);
}
+ if (any_of(ArgLocs,
+ [](CCValAssign &VA) { return VA.getLocVT().isScalableVector(); }))
+ MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
+
if (IsVarArg) {
ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs);
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SDLoc &DL, SelectionDAG &DAG) const {
- const MachineFunction &MF = DAG.getMachineFunction();
+ MachineFunction &MF = DAG.getMachineFunction();
const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
// Stores the assignment of the return value to a location.
RetOps.push_back(Glue);
}
+ if (any_of(RVLocs,
+ [](CCValAssign &VA) { return VA.getLocVT().isScalableVector(); }))
+ MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
+
unsigned RetOpc = RISCVISD::RET_FLAG;
// Interrupt service routines use different return instructions.
const Function &Func = DAG.getMachineFunction().getFunction();
uint64_t RVVPadding = 0;
/// Size of stack frame to save callee saved registers
unsigned CalleeSavedStackSize = 0;
+ /// Is there any vector argument or return?
+ bool IsVectorCall = false;
/// Registers that have been sign extended from i32.
SmallVector<Register, 8> SExt32Registers;
void addSExt32Register(Register Reg);
bool isSExt32Register(Register Reg) const;
+
+ bool isVectorCall() const { return IsVectorCall; }
+ void setIsVectorCall() { IsVectorCall = true; }
};
} // end namespace llvm
--- /dev/null
+; RUN: llc -mtriple=riscv64 -mattr=+v -o - %s | FileCheck %s --check-prefix=CHECK-ASM
+; RUN: llc -mtriple=riscv64 -mattr=+v -filetype=obj -o - %s \
+; RUN: | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-OBJ
+
+define i32 @base_cc() {
+; CHECK-ASM-LABEL: base_cc:
+; CHECK-ASM-NOT: .variant_cc
+; CHECK-OBJ-LABEL: Name: base_cc
+; CHECK-OBJ: Other: 0
+ ret i32 42
+}
+
+define <4 x i32> @fixed_vector_cc_1(<4 x i32> %arg) {
+; CHECK-ASM: .variant_cc fixed_vector_cc_1
+; CHECK-ASM-NEXT: fixed_vector_cc_1:
+; CHECK-OBJ-LABEL: Name: fixed_vector_cc_1
+; CHECK-OBJ: Other [ (0x80)
+ ret <4 x i32> %arg
+}
+
+define <vscale x 4 x i32> @rvv_vector_cc_1() {
+; CHECK-ASM: .variant_cc rvv_vector_cc_1
+; CHECK-ASM-NEXT: rvv_vector_cc_1:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_1
+; CHECK-OBJ: Other [ (0x80)
+ ret <vscale x 4 x i32> undef
+}
+
+define <vscale x 4 x i1> @rvv_vector_cc_2() {
+; CHECK-ASM: .variant_cc rvv_vector_cc_2
+; CHECK-ASM-NEXT: rvv_vector_cc_2:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_2
+; CHECK-OBJ: Other [ (0x80)
+ ret <vscale x 4 x i1> undef
+}
+
+define void @rvv_vector_cc_3(<vscale x 4 x i32> %arg) {
+; CHECK-ASM: .variant_cc rvv_vector_cc_3
+; CHECK-ASM-NEXT: rvv_vector_cc_3:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_3
+; CHECK-OBJ: Other [ (0x80)
+ ret void
+}
+
+define void @rvv_vector_cc_4(<vscale x 4 x i1> %arg) {
+; CHECK-ASM: .variant_cc rvv_vector_cc_4
+; CHECK-ASM-NEXT: rvv_vector_cc_4:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_4
+; CHECK-OBJ: Other [ (0x80)
+ ret void
+}