ARM: dts: qcom: msm8974: add interconnect nodes

Add interconnect nodes that's needed to support bus scaling.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Link: https://lore.kernel.org/r/20191024103140.10077-5-masneyb@onstation.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 3bbb8a1..902e26b 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
+#include <dt-bindings/interconnect/qcom,msm8974.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
@@ -1198,6 +1199,60 @@
                        };
                };
 
+               bimc: interconnect@fc380000 {
+                       reg = <0xfc380000 0x6a000>;
+                       compatible = "qcom,msm8974-bimc";
+                       #interconnect-cells = <1>;
+                       clock-names = "bus", "bus_a";
+                       clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+                                <&rpmcc RPM_SMD_BIMC_A_CLK>;
+               };
+
+               snoc: interconnect@fc460000 {
+                       reg = <0xfc460000 0x4000>;
+                       compatible = "qcom,msm8974-snoc";
+                       #interconnect-cells = <1>;
+                       clock-names = "bus", "bus_a";
+                       clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+                                <&rpmcc RPM_SMD_SNOC_A_CLK>;
+               };
+
+               pnoc: interconnect@fc468000 {
+                       reg = <0xfc468000 0x4000>;
+                       compatible = "qcom,msm8974-pnoc";
+                       #interconnect-cells = <1>;
+                       clock-names = "bus", "bus_a";
+                       clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
+                                <&rpmcc RPM_SMD_PNOC_A_CLK>;
+               };
+
+               ocmemnoc: interconnect@fc470000 {
+                       reg = <0xfc470000 0x4000>;
+                       compatible = "qcom,msm8974-ocmemnoc";
+                       #interconnect-cells = <1>;
+                       clock-names = "bus", "bus_a";
+                       clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+                                <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
+               };
+
+               mmssnoc: interconnect@fc478000 {
+                       reg = <0xfc478000 0x4000>;
+                       compatible = "qcom,msm8974-mmssnoc";
+                       #interconnect-cells = <1>;
+                       clock-names = "bus", "bus_a";
+                       clocks = <&mmcc MMSS_S0_AXI_CLK>,
+                                <&mmcc MMSS_S0_AXI_CLK>;
+               };
+
+               cnoc: interconnect@fc480000 {
+                       reg = <0xfc480000 0x4000>;
+                       compatible = "qcom,msm8974-cnoc";
+                       #interconnect-cells = <1>;
+                       clock-names = "bus", "bus_a";
+                       clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+                                <&rpmcc RPM_SMD_CNOC_A_CLK>;
+               };
+
                mdss: mdss@fd900000 {
                        status = "disabled";
 
@@ -1244,6 +1299,9 @@
                                              "core",
                                              "vsync";
 
+                               interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
+                               interconnect-names = "mdp0-mem";
+
                                ports {
                                        #address-cells = <1>;
                                        #size-cells = <0>;