drm/i915/chv: Don't use PCS group access reads

All PCS groups access reads return 0xffffffff, so we can't use group
access for RMW cycles. Instead target each spline separately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Fight conflict with misplaced ; .... ARGH!]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d1d287..eba35bc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -659,6 +659,13 @@ enum punit_power_well {
 #define   DPIO_PCS_TX_LANE1_RESET      (1<<7)
 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
 
+#define _VLV_PCS01_DW0_CH0             0x200
+#define _VLV_PCS23_DW0_CH0             0x400
+#define _VLV_PCS01_DW0_CH1             0x2600
+#define _VLV_PCS23_DW0_CH1             0x2800
+#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
 #define _VLV_PCS_DW1_CH0               0x8204
 #define _VLV_PCS_DW1_CH1               0x8404
 #define   CHV_PCS_REQ_SOFTRESET_EN     (1<<23)
@@ -668,6 +675,13 @@ enum punit_power_well {
 #define   DPIO_PCS_CLK_SOFT_RESET      (1<<5)
 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
 
+#define _VLV_PCS01_DW1_CH0             0x204
+#define _VLV_PCS23_DW1_CH0             0x404
+#define _VLV_PCS01_DW1_CH1             0x2604
+#define _VLV_PCS23_DW1_CH1             0x2804
+#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
+#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
+
 #define _VLV_PCS_DW8_CH0               0x8220
 #define _VLV_PCS_DW8_CH1               0x8420
 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 37638f8..d98de3c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1882,13 +1882,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
        mutex_lock(&dev_priv->dpio_lock);
 
        /* Propagate soft reset to data lane reset */
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
        val |= CHV_PCS_REQ_SOFTRESET_EN;
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
 
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+       val |= CHV_PCS_REQ_SOFTRESET_EN;
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+       val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
        val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
        mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -2027,13 +2035,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
        mutex_lock(&dev_priv->dpio_lock);
 
        /* Deassert soft data lane reset*/
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
        val |= CHV_PCS_REQ_SOFTRESET_EN;
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+       val |= CHV_PCS_REQ_SOFTRESET_EN;
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+       val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
 
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
        val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
        /* Program Tx lane latency optimal setting*/
        for (i = 0; i < 4; i++) {

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f66c7a2..b976255 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1259,13 +1259,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
        mutex_lock(&dev_priv->dpio_lock);
 
        /* Propagate soft reset to data lane reset */
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
        val |= CHV_PCS_REQ_SOFTRESET_EN;
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
 
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+       val |= CHV_PCS_REQ_SOFTRESET_EN;
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+       val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
        val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
        mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -1285,13 +1293,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
        mutex_lock(&dev_priv->dpio_lock);
 
        /* Deassert soft data lane reset*/
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
        val |= CHV_PCS_REQ_SOFTRESET_EN;
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+       val |= CHV_PCS_REQ_SOFTRESET_EN;
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+       val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
 
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
        val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
        /* Program Tx latency optimal setting */
        for (i = 0; i < 4; i++) {