Davinci: Configurable NAND chip selects
authorNick Thompson <nick.thompson@gefanuc.com>
Sat, 12 Dec 2009 17:12:26 +0000 (12:12 -0500)
committerTom Rix <Tom.Rix@windriver.com>
Mon, 4 Jan 2010 14:48:17 +0000 (08:48 -0600)
Davinci: Configurable NAND chip selects

Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
drivers/mtd/nand/davinci_nand.c
include/asm-arm/arch-davinci/emif_defs.h
include/configs/davinci_dm355evm.h
include/configs/davinci_dm355leopard.h
include/configs/davinci_dm365evm.h
include/configs/davinci_dm6467evm.h
include/configs/davinci_dvevm.h
include/configs/davinci_schmoogie.h
include/configs/davinci_sffsdr.h
include/configs/davinci_sonata.h

index 41a9568..1ad802a 100644 (file)
@@ -82,26 +82,20 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c
 
 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 {
-       int             dummy;
+       u_int32_t       val;
 
-       dummy = emif_regs->NANDF1ECC;
+       (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
 
-       /* FIXME:  only chipselect 0 is supported for now */
-       emif_regs->NANDFCR |= 1 << 8;
+       val = readl(&emif_regs->NANDFCR);
+       val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+       writel(val, &emif_regs->NANDFCR);
 }
 
 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
 {
        u_int32_t       ecc = 0;
 
-       if (region == 1)
-               ecc = emif_regs->NANDF1ECC;
-       else if (region == 2)
-               ecc = emif_regs->NANDF2ECC;
-       else if (region == 3)
-               ecc = emif_regs->NANDF3ECC;
-       else if (region == 4)
-               ecc = emif_regs->NANDF4ECC;
+       ecc = readl(&(emif_regs->NANDFECC[region - 1]));
 
        return(ecc);
 }
@@ -223,8 +217,11 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
                 * Start a new ECC calculation for reading or writing 512 bytes
                 * of data.
                 */
-               val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
-               emif_regs->NANDFCR = val;
+               val = readl(&emif_regs->NANDFCR);
+               val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
+               val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+               val |= DAVINCI_NANDFCR_4BIT_ECC_START;
+               writel(val, &emif_regs->NANDFCR);
                break;
        case NAND_ECC_READSYN:
                val = emif_regs->NAND4BITECC1;
index c91e30c..d67292f 100644 (file)
@@ -51,10 +51,7 @@ typedef struct {
        dv_reg          NANDFCR;
        dv_reg          NANDFSR;
        u_int8_t        RSVD1[8];
-       dv_reg          NANDF1ECC;
-       dv_reg          NANDF2ECC;
-       dv_reg          NANDF3ECC;
-       dv_reg          NANDF4ECC;
+       dv_reg          NANDFECC[4];
        u_int8_t        RSVD2[60];
        dv_reg          NAND4BITECCLOAD;
        dv_reg          NAND4BITECC1;
@@ -68,4 +65,13 @@ typedef struct {
 } emif_registers;
 
 typedef emif_registers *emifregs;
+
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK              (3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)                        ((n-2) << 4)
+
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n)              (1 << (8 + (n-2)))
+
+#define DAVINCI_NANDFCR_4BIT_ECC_START                 (1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START                        (1 << 13)
+
 #endif
index d092fb8..37011c0 100644 (file)
@@ -66,6 +66,7 @@
 
 /* NAND: socketed, two chipselects, normally 2 GBytes */
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_PAGE_2K
index ca3dea4..e09fb75 100644 (file)
@@ -65,6 +65,7 @@
 
 /* NAND */
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_HW_ECC
 
index 4916077..c6e1d10 100644 (file)
@@ -74,6 +74,7 @@
 
 /* NAND: socketed, two chipselects, normally 2 GBytes */
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_PAGE_2K
index ce2d7c4..ddc5990 100644 (file)
@@ -75,6 +75,7 @@
 #define CONFIG_SYS_NO_FLASH
 #ifdef CONFIG_SYS_USE_NAND
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #undef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE                        (16 << 10)      /* 16 KiB */
index f7d2399..5774df5 100644 (file)
 /*=====================*/
 #ifdef CONFIG_SYS_USE_NAND
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #undef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND          /* U-Boot env in NAND Flash  */
index 47db2aa..3972ebc 100644 (file)
@@ -83,6 +83,7 @@
 #undef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #define CONFIG_ENV_IS_IN_NAND          /* U-Boot env in NAND Flash  */
 #define CONFIG_ENV_SECT_SIZE   2048    /* Env sector Size */
 #define CONFIG_ENV_SIZE                (128 << 10)     /* 128 KiB */
index f24eb7a..94be9dc 100644 (file)
@@ -78,6 +78,7 @@
 #undef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #define CONFIG_ENV_IS_IN_NAND          /* U-Boot env in NAND Flash  */
 #define CONFIG_ENV_SECT_SIZE   2048    /* Env sector Size */
 #define CONFIG_ENV_SIZE                (128 << 10)     /* 128 KiB */
index 5a55c56..490821a 100644 (file)
 /*=====================*/
 #ifdef CONFIG_SYS_USE_NAND
 #define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS             2
 #undef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND          /* U-Boot env in NAND Flash  */