x86: Optimize EVEX vector load/store instructions

When there is no write mask, we can encode lower 16 128-bit/256-bit
EVEX vector register load and store instructions as VEX vector register
load and store instructions with -O1.

gas/

	PR gas/24348
	* config/tc-i386.c (optimize_encoding): Encode 128-bit and
	256-bit EVEX vector register load/store instructions as VEX
	vector register load/store instructions for -O1.
	* doc/c-i386.texi: Update -O1 documentation.
	* testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
	* testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
	load/store instructions.
	* testsuite/gas/i386/optimize-2.s: Likewise.
	* testsuite/gas/i386/optimize-3.s: Likewise.
	* testsuite/gas/i386/optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-3.d: Likewise.
	* testsuite/gas/i386/optimize-4.d: Likewise.
	* testsuite/gas/i386/optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
	* testsuite/gas/i386/optimize-7.d: New file.
	* testsuite/gas/i386/optimize-7.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-8.s: Likewise.

opcodes/

	PR gas/24348
	* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
	vmovdqu16, vmovdqu32 and vmovdqu64.
	* i386-tbl.h: Regenerated.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3ab51c7..7c09862 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,38 @@
 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 
+       PR gas/24348
+       * config/tc-i386.c (optimize_encoding): Encode 128-bit and
+       256-bit EVEX vector register load/store instructions as VEX
+       vector register load/store instructions for -O1.
+       * doc/c-i386.texi: Update -O1 documentation.
+       * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
+       * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
+       load/store instructions.
+       * testsuite/gas/i386/optimize-2.s: Likewise.
+       * testsuite/gas/i386/optimize-3.s: Likewise.
+       * testsuite/gas/i386/optimize-5.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
+       * testsuite/gas/i386/optimize-1.d: Updated.
+       * testsuite/gas/i386/optimize-2.d: Likewise.
+       * testsuite/gas/i386/optimize-3.d: Likewise.
+       * testsuite/gas/i386/optimize-4.d: Likewise.
+       * testsuite/gas/i386/optimize-5.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+       * testsuite/gas/i386/optimize-7.d: New file.
+       * testsuite/gas/i386/optimize-7.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-8.s: Likewise.
+
+2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
+
        * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
        VEX/EVEX vector register clearing instructions with 128-bit VEX
        vector register clearing instructions at -O1.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 856c18d..fa06075 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4075,6 +4075,56 @@ optimize_encoding (void)
            i.types[j].bitfield.ymmword = 0;
          }
     }
+  else if ((cpu_arch_flags.bitfield.cpuavx
+           || cpu_arch_isa_flags.bitfield.cpuavx)
+          && i.vec_encoding != vex_encoding_evex
+          && !i.types[0].bitfield.zmmword
+          && !i.mask
+          && is_evex_encoding (&i.tm)
+          && (i.tm.base_opcode == 0x666f
+              || (i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0x666f
+              || i.tm.base_opcode == 0xf36f
+              || (i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0xf36f
+              || i.tm.base_opcode == 0xf26f
+              || (i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0xf26f)
+          && i.tm.extension_opcode == None)
+    {
+      /* Optimize: -O1:
+          VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
+          vmovdqu32 and vmovdqu64:
+            EVEX VOP %xmmM, %xmmN
+              -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
+            EVEX VOP %ymmM, %ymmN
+              -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
+            EVEX VOP %xmmM, mem
+              -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
+            EVEX VOP %ymmM, mem
+              -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
+            EVEX VOP mem, %xmmN
+              -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
+            EVEX VOP mem, %ymmN
+              -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
+       */
+      if (i.tm.base_opcode == 0xf26f)
+       i.tm.base_opcode = 0xf36f;
+      else if ((i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0xf26f)
+       i.tm.base_opcode = 0xf36f ^ Opcode_SIMD_IntD;
+      i.tm.opcode_modifier.vex
+       = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
+      i.tm.opcode_modifier.vexw = VEXW0;
+      i.tm.opcode_modifier.evex = 0;
+      i.tm.opcode_modifier.masking = 0;
+      i.tm.opcode_modifier.disp8memshift = 0;
+      i.memshift = 0;
+      for (j = 0; j < 2; j++)
+       if (operand_type_check (i.types[j], disp)
+           && i.op[j].disps->X_op == O_constant)
+         {
+           i.types[j].bitfield.disp8
+             = fits_in_disp8 (i.op[j].disps->X_add_number);
+           break;
+         }
+    }
 }
 
 /* This is the guts of the machine-dependent assembler.  LINE points to a

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 7e5f5c2..4acd5ff 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -456,7 +456,9 @@ immediate as 32-bit register load instructions with 31-bit or 32-bits
 immediates, encode 64-bit register clearing instructions with 32-bit
 register clearing instructions and encode 256-bit/512-bit VEX/EVEX
 vector register clearing instructions with 128-bit VEX vector register
-clearing instructions.  @samp{-O2} includes @samp{-O1} optimization plus
+clearing instructions as well as encode 128-bit/256-bit EVEX vector
+register load/store instructions with VEX vector register load/store
+instructions.  @samp{-O2} includes @samp{-O1} optimization plus
 encodes 256-bit/512-bit EVEX vector register clearing instructions with
 128-bit EVEX vector register clearing instructions.
 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit

diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 798bfb5..3067b4a 100644 (file)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -476,6 +476,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "optimize-6a"
     run_dump_test "optimize-6b"
     run_dump_test "optimize-6c"
+    run_dump_test "optimize-7"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -990,6 +991,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-optimize-7a"
     run_dump_test "x86-64-optimize-7b"
     run_dump_test "x86-64-optimize-7c"
+    run_dump_test "x86-64-optimize-8"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]

diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d
index 4358c19..70c802c 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-1.d
+++ b/gas/testsuite/gas/i386/optimize-1.d
@@ -62,4 +62,40 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-1.s b/gas/testsuite/gas/i386/optimize-1.s
index f61a176..6dcfbc2 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-1.s
+++ b/gas/testsuite/gas/i386/optimize-1.s
@@ -72,3 +72,45 @@ _start:
 
        kandnd %k1, %k1, %k5
        kandnq %k1, %k1, %k5
+
+       vmovdqa32       %xmm1, %xmm2
+       vmovdqa64       %xmm1, %xmm2
+       vmovdqu8        %xmm1, %xmm2
+       vmovdqu16       %xmm1, %xmm2
+       vmovdqu32       %xmm1, %xmm2
+       vmovdqu64       %xmm1, %xmm2
+
+       vmovdqa32       127(%eax), %xmm2
+       vmovdqa64       127(%eax), %xmm2
+       vmovdqu8        127(%eax), %xmm2
+       vmovdqu16       127(%eax), %xmm2
+       vmovdqu32       127(%eax), %xmm2
+       vmovdqu64       127(%eax), %xmm2
+
+       vmovdqa32       %xmm1, 128(%eax)
+       vmovdqa64       %xmm1, 128(%eax)
+       vmovdqu8        %xmm1, 128(%eax)
+       vmovdqu16       %xmm1, 128(%eax)
+       vmovdqu32       %xmm1, 128(%eax)
+       vmovdqu64       %xmm1, 128(%eax)
+
+       vmovdqa32       %ymm1, %ymm2
+       vmovdqa64       %ymm1, %ymm2
+       vmovdqu8        %ymm1, %ymm2
+       vmovdqu16       %ymm1, %ymm2
+       vmovdqu32       %ymm1, %ymm2
+       vmovdqu64       %ymm1, %ymm2
+
+       vmovdqa32       127(%eax), %ymm2
+       vmovdqa64       127(%eax), %ymm2
+       vmovdqu8        127(%eax), %ymm2
+       vmovdqu16       127(%eax), %ymm2
+       vmovdqu32       127(%eax), %ymm2
+       vmovdqu64       127(%eax), %ymm2
+
+       vmovdqa32       %ymm1, 128(%eax)
+       vmovdqa64       %ymm1, 128(%eax)
+       vmovdqu8        %ymm1, 128(%eax)
+       vmovdqu16       %ymm1, 128(%eax)
+       vmovdqu32       %ymm1, 128(%eax)
+       vmovdqu64       %ymm1, 128(%eax)

diff --git a/gas/testsuite/gas/i386/optimize-1a.d b/gas/testsuite/gas/i386/optimize-1a.d
index e6e6d81..cee2383 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-1a.d
+++ b/gas/testsuite/gas/i386/optimize-1a.d
@@ -63,4 +63,40 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-2.d b/gas/testsuite/gas/i386/optimize-2.d
index e8a5169..19467f5 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-2.d
+++ b/gas/testsuite/gas/i386/optimize-2.d
@@ -17,4 +17,76 @@ Disassembly of section .text:
  +[a-f0-9]+:   f7 c7 7f 00 00 00       test   \$0x7f,%edi
  +[a-f0-9]+:   66 f7 c7 7f 00          test   \$0x7f,%di
  +[a-f0-9]+:   c5 f1 55 e9             vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   62 f1 7d 48 6f d1       vmovdqa32 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 fd 48 6f d1       vmovdqa64 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 7f 48 6f d1       vmovdqu8 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 ff 48 6f d1       vmovdqu16 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 7e 48 6f d1       vmovdqu32 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 fe 48 6f d1       vmovdqu64 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 fd 28 6f d1       vmovdqa64 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 7f 08 6f d1       vmovdqu8 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 ff 08 6f d1       vmovdqu16 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7e 08 6f d1       vmovdqu32 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 fe 08 6f d1       vmovdqu64 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7d 29 6f d1       vmovdqa32 %ymm1,%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fd 29 6f d1       vmovdqa64 %ymm1,%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7f 09 6f d1       vmovdqu8 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 ff 09 6f d1       vmovdqu16 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7e 09 6f d1       vmovdqu32 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fe 09 6f d1       vmovdqu64 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7d 29 6f 10       vmovdqa32 \(%eax\),%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fd 29 6f 10       vmovdqa64 \(%eax\),%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7f 09 6f 10       vmovdqu8 \(%eax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 ff 09 6f 10       vmovdqu16 \(%eax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7e 09 6f 10       vmovdqu32 \(%eax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fe 09 6f 10       vmovdqu64 \(%eax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7d 29 7f 08       vmovdqa32 %ymm1,\(%eax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 fd 29 7f 08       vmovdqa64 %ymm1,\(%eax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 7f 09 7f 08       vmovdqu8 %xmm1,\(%eax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 ff 09 7f 08       vmovdqu16 %xmm1,\(%eax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 7e 09 7f 08       vmovdqu32 %xmm1,\(%eax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 fe 09 7f 08       vmovdqu64 %xmm1,\(%eax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 7d 89 6f d1       vmovdqa32 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 fd 89 6f d1       vmovdqa64 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 7f 89 6f d1       vmovdqu8 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 ff 89 6f d1       vmovdqu16 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 7e 89 6f d1       vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 fe 89 6f d1       vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-2.s b/gas/testsuite/gas/i386/optimize-2.s
index c9b57a8..0a4fb23 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-2.s
+++ b/gas/testsuite/gas/i386/optimize-2.s
@@ -13,3 +13,87 @@ _start:
        test    $0x7f, %di
 
        vandnpd %zmm1, %zmm1, %zmm5
+
+       vmovdqa32       %xmm1, %xmm2
+       vmovdqa64       %xmm1, %xmm2
+       vmovdqu8        %xmm1, %xmm2
+       vmovdqu16       %xmm1, %xmm2
+       vmovdqu32       %xmm1, %xmm2
+       vmovdqu64       %xmm1, %xmm2
+
+       vmovdqa32       127(%eax), %xmm2
+       vmovdqa64       127(%eax), %xmm2
+       vmovdqu8        127(%eax), %xmm2
+       vmovdqu16       127(%eax), %xmm2
+       vmovdqu32       127(%eax), %xmm2
+       vmovdqu64       127(%eax), %xmm2
+
+       vmovdqa32       %xmm1, 128(%eax)
+       vmovdqa64       %xmm1, 128(%eax)
+       vmovdqu8        %xmm1, 128(%eax)
+       vmovdqu16       %xmm1, 128(%eax)
+       vmovdqu32       %xmm1, 128(%eax)
+       vmovdqu64       %xmm1, 128(%eax)
+
+       vmovdqa32       %ymm1, %ymm2
+       vmovdqa64       %ymm1, %ymm2
+       vmovdqu8        %ymm1, %ymm2
+       vmovdqu16       %ymm1, %ymm2
+       vmovdqu32       %ymm1, %ymm2
+       vmovdqu64       %ymm1, %ymm2
+
+       vmovdqa32       127(%eax), %ymm2
+       vmovdqa64       127(%eax), %ymm2
+       vmovdqu8        127(%eax), %ymm2
+       vmovdqu16       127(%eax), %ymm2
+       vmovdqu32       127(%eax), %ymm2
+       vmovdqu64       127(%eax), %ymm2
+
+       vmovdqa32       %ymm1, 128(%eax)
+       vmovdqa64       %ymm1, 128(%eax)
+       vmovdqu8        %ymm1, 128(%eax)
+       vmovdqu16       %ymm1, 128(%eax)
+       vmovdqu32       %ymm1, 128(%eax)
+       vmovdqu64       %ymm1, 128(%eax)
+
+       vmovdqa32       %zmm1, %zmm2
+       vmovdqa64       %zmm1, %zmm2
+       vmovdqu8        %zmm1, %zmm2
+       vmovdqu16       %zmm1, %zmm2
+       vmovdqu32       %zmm1, %zmm2
+       vmovdqu64       %zmm1, %zmm2
+
+       {evex} vmovdqa32        %ymm1, %ymm2
+       {evex} vmovdqa64        %ymm1, %ymm2
+       {evex} vmovdqu8         %xmm1, %xmm2
+       {evex} vmovdqu16        %xmm1, %xmm2
+       {evex} vmovdqu32        %xmm1, %xmm2
+       {evex} vmovdqu64        %xmm1, %xmm2
+
+       vmovdqa32       %ymm1, %ymm2{%k1}
+       vmovdqa64       %ymm1, %ymm2{%k1}
+       vmovdqu8        %xmm1, %xmm2{%k1}
+       vmovdqu16       %xmm1, %xmm2{%k1}
+       vmovdqu32       %xmm1, %xmm2{%k1}
+       vmovdqu64       %xmm1, %xmm2{%k1}
+
+       vmovdqa32       (%eax), %ymm2{%k1}
+       vmovdqa64       (%eax), %ymm2{%k1}
+       vmovdqu8        (%eax), %xmm2{%k1}
+       vmovdqu16       (%eax), %xmm2{%k1}
+       vmovdqu32       (%eax), %xmm2{%k1}
+       vmovdqu64       (%eax), %xmm2{%k1}
+
+       vmovdqa32       %ymm1, (%eax){%k1}
+       vmovdqa64       %ymm1, (%eax){%k1}
+       vmovdqu8        %xmm1, (%eax){%k1}
+       vmovdqu16       %xmm1, (%eax){%k1}
+       vmovdqu32       %xmm1, (%eax){%k1}
+       vmovdqu64       %xmm1, (%eax){%k1}
+
+       vmovdqa32       %xmm1, %xmm2{%k1}{z}
+       vmovdqa64       %xmm1, %xmm2{%k1}{z}
+       vmovdqu8        %xmm1, %xmm2{%k1}{z}
+       vmovdqu16       %xmm1, %xmm2{%k1}{z}
+       vmovdqu32       %xmm1, %xmm2{%k1}{z}
+       vmovdqu64       %xmm1, %xmm2{%k1}{z}

diff --git a/gas/testsuite/gas/i386/optimize-3.d b/gas/testsuite/gas/i386/optimize-3.d
index f251a36..cd43243 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-3.d
+++ b/gas/testsuite/gas/i386/optimize-3.d
@@ -9,4 +9,10 @@ Disassembly of section .text:
 
 0+ <_start>:
  +[a-f0-9]+:   a9 7f 00 00 00          test   \$0x7f,%eax
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 fd 28 6f d1       vmovdqa64 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 7f 08 6f d1       vmovdqu8 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 ff 08 6f d1       vmovdqu16 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7e 08 6f d1       vmovdqu32 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 fe 08 6f d1       vmovdqu64 %xmm1,%xmm2
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-3.s b/gas/testsuite/gas/i386/optimize-3.s
index 536bf0c..a70893c 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-3.s
+++ b/gas/testsuite/gas/i386/optimize-3.s
@@ -4,3 +4,10 @@
        .text
 _start:
        {nooptimize} testl $0x7f, %eax
+
+       {nooptimize} vmovdqa32  %ymm1, %ymm2
+       {nooptimize} vmovdqa64  %ymm1, %ymm2
+       {nooptimize} vmovdqu8   %xmm1, %xmm2
+       {nooptimize} vmovdqu16  %xmm1, %xmm2
+       {nooptimize} vmovdqu32  %xmm1, %xmm2
+       {nooptimize} vmovdqu64  %xmm1, %xmm2

diff --git a/gas/testsuite/gas/i386/optimize-4.d b/gas/testsuite/gas/i386/optimize-4.d
index 9f99dad..2df8465 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-4.d
+++ b/gas/testsuite/gas/i386/optimize-4.d
@@ -62,6 +62,42 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-5.d b/gas/testsuite/gas/i386/optimize-5.d
index cfd0df0..ecc1ab1 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-5.d
+++ b/gas/testsuite/gas/i386/optimize-5.d
@@ -62,6 +62,48 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
  +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%eax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%eax\)
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 fd 28 6f d1       vmovdqa64 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 7f 08 6f d1       vmovdqu8 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 ff 08 6f d1       vmovdqu16 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7e 08 6f d1       vmovdqu32 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 fe 08 6f d1       vmovdqu64 %xmm1,%xmm2
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-5.s b/gas/testsuite/gas/i386/optimize-5.s
index 66c762b..77d60ed 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-5.s
+++ b/gas/testsuite/gas/i386/optimize-5.s
@@ -6,3 +6,10 @@
 
        {evex} vandnpd %zmm1, %zmm1, %zmm5
        {evex} vandnpd %ymm1, %ymm1, %ymm5
+
+       {evex} vmovdqa32        %ymm1, %ymm2
+       {evex} vmovdqa64        %ymm1, %ymm2
+       {evex} vmovdqu8         %xmm1, %xmm2
+       {evex} vmovdqu16        %xmm1, %xmm2
+       {evex} vmovdqu32        %xmm1, %xmm2
+       {evex} vmovdqu64        %xmm1, %xmm2

diff --git a/gas/testsuite/gas/i386/optimize-7.d b/gas/testsuite/gas/i386/optimize-7.d
new file mode 100644 (file)
index 0000000..92ca7a6
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-7.d
@@ -0,0 +1,12 @@
+#as: -O2 -march=+noavx
+#objdump: -drw
+#name: optimized encoding 7 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+#pass

diff --git a/gas/testsuite/gas/i386/optimize-7.s b/gas/testsuite/gas/i386/optimize-7.s
new file mode 100644 (file)
index 0000000..261b4af
--- /dev/null
+++ b/gas/testsuite/gas/i386/optimize-7.s
@@ -0,0 +1,6 @@
+# Check instructions with optimized encoding
+
+       .allow_index_reg
+       .text
+_start:
+       vmovdqa32       %ymm1, %ymm2

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.d b/gas/testsuite/gas/i386/x86-64-optimize-2.d
index fa031e8..7d7340f 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d
@@ -106,4 +106,52 @@ Disassembly of section .text:
  +[a-f0-9]+:   62 e1 f5 08 fb c1       vpsubq %xmm1,%xmm1,%xmm16
  +[a-f0-9]+:   62 b1 f5 00 fb c9       vpsubq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:   62 b1 f5 00 fb c9       vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.s b/gas/testsuite/gas/i386/x86-64-optimize-2.s
index 10ce788..1275610 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.s
@@ -114,3 +114,59 @@ _start:
        vpsubq %ymm1, %ymm1, %ymm16
        vpsubq %zmm17, %zmm17, %zmm1
        vpsubq %ymm17, %ymm17, %ymm1
+
+       vmovdqa32       %xmm1, %xmm2
+       vmovdqa64       %xmm1, %xmm2
+       vmovdqu8        %xmm1, %xmm2
+       vmovdqu16       %xmm1, %xmm2
+       vmovdqu32       %xmm1, %xmm2
+       vmovdqu64       %xmm1, %xmm2
+
+       vmovdqa32       %xmm11, %xmm12
+       vmovdqa64       %xmm11, %xmm12
+       vmovdqu8        %xmm11, %xmm12
+       vmovdqu16       %xmm11, %xmm12
+       vmovdqu32       %xmm11, %xmm12
+       vmovdqu64       %xmm11, %xmm12
+
+       vmovdqa32       127(%rax), %xmm2
+       vmovdqa64       127(%rax), %xmm2
+       vmovdqu8        127(%rax), %xmm2
+       vmovdqu16       127(%rax), %xmm2
+       vmovdqu32       127(%rax), %xmm2
+       vmovdqu64       127(%rax), %xmm2
+
+       vmovdqa32       %xmm1, 128(%rax)
+       vmovdqa64       %xmm1, 128(%rax)
+       vmovdqu8        %xmm1, 128(%rax)
+       vmovdqu16       %xmm1, 128(%rax)
+       vmovdqu32       %xmm1, 128(%rax)
+       vmovdqu64       %xmm1, 128(%rax)
+
+       vmovdqa32       %ymm1, %ymm2
+       vmovdqa64       %ymm1, %ymm2
+       vmovdqu8        %ymm1, %ymm2
+       vmovdqu16       %ymm1, %ymm2
+       vmovdqu32       %ymm1, %ymm2
+       vmovdqu64       %ymm1, %ymm2
+
+       vmovdqa32       %ymm11, %ymm12
+       vmovdqa64       %ymm11, %ymm12
+       vmovdqu8        %ymm11, %ymm12
+       vmovdqu16       %ymm11, %ymm12
+       vmovdqu32       %ymm11, %ymm12
+       vmovdqu64       %ymm11, %ymm12
+
+       vmovdqa32       127(%rax), %ymm2
+       vmovdqa64       127(%rax), %ymm2
+       vmovdqu8        127(%rax), %ymm2
+       vmovdqu16       127(%rax), %ymm2
+       vmovdqu32       127(%rax), %ymm2
+       vmovdqu64       127(%rax), %ymm2
+
+       vmovdqa32       %ymm1, 128(%rax)
+       vmovdqa64       %ymm1, 128(%rax)
+       vmovdqu8        %ymm1, 128(%rax)
+       vmovdqu16       %ymm1, 128(%rax)
+       vmovdqu32       %ymm1, 128(%rax)
+       vmovdqu64       %ymm1, 128(%rax)

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2a.d b/gas/testsuite/gas/i386/x86-64-optimize-2a.d
index 9c6466d..532a145 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-2a.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2a.d
@@ -107,4 +107,52 @@ Disassembly of section .text:
  +[a-f0-9]+:   62 e1 f5 28 fb c1       vpsubq %ymm1,%ymm1,%ymm16
  +[a-f0-9]+:   62 b1 f5 40 fb c9       vpsubq %zmm17,%zmm17,%zmm1
  +[a-f0-9]+:   62 b1 f5 20 fb c9       vpsubq %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-3.d b/gas/testsuite/gas/i386/x86-64-optimize-3.d
index f85c0af..74336a4 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-3.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3.d
@@ -25,4 +25,94 @@ Disassembly of section .text:
  +[a-f0-9]+:   41 f6 c1 7f             test   \$0x7f,%r9b
  +[a-f0-9]+:   41 f6 c1 7f             test   \$0x7f,%r9b
  +[a-f0-9]+:   c5 f1 55 e9             vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 b1 7d 08 6f d5       vmovdqa32 %xmm21,%xmm2
+ +[a-f0-9]+:   62 b1 fd 08 6f d5       vmovdqa64 %xmm21,%xmm2
+ +[a-f0-9]+:   62 b1 7f 08 6f d5       vmovdqu8 %xmm21,%xmm2
+ +[a-f0-9]+:   62 b1 ff 08 6f d5       vmovdqu16 %xmm21,%xmm2
+ +[a-f0-9]+:   62 b1 7e 08 6f d5       vmovdqu32 %xmm21,%xmm2
+ +[a-f0-9]+:   62 b1 fe 08 6f d5       vmovdqu64 %xmm21,%xmm2
+ +[a-f0-9]+:   62 f1 7d 48 6f d1       vmovdqa32 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 fd 48 6f d1       vmovdqa64 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 7f 48 6f d1       vmovdqu8 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 ff 48 6f d1       vmovdqu16 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 7e 48 6f d1       vmovdqu32 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 fe 48 6f d1       vmovdqu64 %zmm1,%zmm2
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 fd 28 6f d1       vmovdqa64 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 7f 08 6f d1       vmovdqu8 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 ff 08 6f d1       vmovdqu16 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7e 08 6f d1       vmovdqu32 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 fe 08 6f d1       vmovdqu64 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7d 29 6f d1       vmovdqa32 %ymm1,%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fd 29 6f d1       vmovdqa64 %ymm1,%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7f 09 6f d1       vmovdqu8 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 ff 09 6f d1       vmovdqu16 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7e 09 6f d1       vmovdqu32 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fe 09 6f d1       vmovdqu64 %xmm1,%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7d 29 6f 10       vmovdqa32 \(%rax\),%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fd 29 6f 10       vmovdqa64 \(%rax\),%ymm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7f 09 6f 10       vmovdqu8 \(%rax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 ff 09 6f 10       vmovdqu16 \(%rax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7e 09 6f 10       vmovdqu32 \(%rax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 fe 09 6f 10       vmovdqu64 \(%rax\),%xmm2\{%k1\}
+ +[a-f0-9]+:   62 f1 7d 29 7f 08       vmovdqa32 %ymm1,\(%rax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 fd 29 7f 08       vmovdqa64 %ymm1,\(%rax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 7f 09 7f 08       vmovdqu8 %xmm1,\(%rax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 ff 09 7f 08       vmovdqu16 %xmm1,\(%rax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 7e 09 7f 08       vmovdqu32 %xmm1,\(%rax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 fe 09 7f 08       vmovdqu64 %xmm1,\(%rax\)\{%k1\}
+ +[a-f0-9]+:   62 f1 7d 89 6f d1       vmovdqa32 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 fd 89 6f d1       vmovdqa64 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 7f 89 6f d1       vmovdqu8 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 ff 89 6f d1       vmovdqu16 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 7e 89 6f d1       vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   62 f1 fe 89 6f d1       vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-3.s b/gas/testsuite/gas/i386/x86-64-optimize-3.s
index 4a52a25..d9c2eb8 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-3.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3.s
@@ -21,3 +21,108 @@ _start:
        test    $0x7f, %r9b
 
        vandnpd %zmm1, %zmm1, %zmm5
+
+       vmovdqa32       %xmm1, %xmm2
+       vmovdqa64       %xmm1, %xmm2
+       vmovdqu8        %xmm1, %xmm2
+       vmovdqu16       %xmm1, %xmm2
+       vmovdqu32       %xmm1, %xmm2
+       vmovdqu64       %xmm1, %xmm2
+
+       vmovdqa32       %xmm11, %xmm12
+       vmovdqa64       %xmm11, %xmm12
+       vmovdqu8        %xmm11, %xmm12
+       vmovdqu16       %xmm11, %xmm12
+       vmovdqu32       %xmm11, %xmm12
+       vmovdqu64       %xmm11, %xmm12
+
+       vmovdqa32       127(%rax), %xmm2
+       vmovdqa64       127(%rax), %xmm2
+       vmovdqu8        127(%rax), %xmm2
+       vmovdqu16       127(%rax), %xmm2
+       vmovdqu32       127(%rax), %xmm2
+       vmovdqu64       127(%rax), %xmm2
+
+       vmovdqa32       %xmm1, 128(%rax)
+       vmovdqa64       %xmm1, 128(%rax)
+       vmovdqu8        %xmm1, 128(%rax)
+       vmovdqu16       %xmm1, 128(%rax)
+       vmovdqu32       %xmm1, 128(%rax)
+       vmovdqu64       %xmm1, 128(%rax)
+
+       vmovdqa32       %ymm1, %ymm2
+       vmovdqa64       %ymm1, %ymm2
+       vmovdqu8        %ymm1, %ymm2
+       vmovdqu16       %ymm1, %ymm2
+       vmovdqu32       %ymm1, %ymm2
+       vmovdqu64       %ymm1, %ymm2
+
+       vmovdqa32       %ymm11, %ymm12
+       vmovdqa64       %ymm11, %ymm12
+       vmovdqu8        %ymm11, %ymm12
+       vmovdqu16       %ymm11, %ymm12
+       vmovdqu32       %ymm11, %ymm12
+       vmovdqu64       %ymm11, %ymm12
+
+       vmovdqa32       127(%rax), %ymm2
+       vmovdqa64       127(%rax), %ymm2
+       vmovdqu8        127(%rax), %ymm2
+       vmovdqu16       127(%rax), %ymm2
+       vmovdqu32       127(%rax), %ymm2
+       vmovdqu64       127(%rax), %ymm2
+
+       vmovdqa32       %ymm1, 128(%rax)
+       vmovdqa64       %ymm1, 128(%rax)
+       vmovdqu8        %ymm1, 128(%rax)
+       vmovdqu16       %ymm1, 128(%rax)
+       vmovdqu32       %ymm1, 128(%rax)
+       vmovdqu64       %ymm1, 128(%rax)
+
+       vmovdqa32       %xmm21, %xmm2
+       vmovdqa64       %xmm21, %xmm2
+       vmovdqu8        %xmm21, %xmm2
+       vmovdqu16       %xmm21, %xmm2
+       vmovdqu32       %xmm21, %xmm2
+       vmovdqu64       %xmm21, %xmm2
+
+       vmovdqa32       %zmm1, %zmm2
+       vmovdqa64       %zmm1, %zmm2
+       vmovdqu8        %zmm1, %zmm2
+       vmovdqu16       %zmm1, %zmm2
+       vmovdqu32       %zmm1, %zmm2
+       vmovdqu64       %zmm1, %zmm2
+
+       {evex} vmovdqa32        %ymm1, %ymm2
+       {evex} vmovdqa64        %ymm1, %ymm2
+       {evex} vmovdqu8         %xmm1, %xmm2
+       {evex} vmovdqu16        %xmm1, %xmm2
+       {evex} vmovdqu32        %xmm1, %xmm2
+       {evex} vmovdqu64        %xmm1, %xmm2
+
+       vmovdqa32       %ymm1, %ymm2{%k1}
+       vmovdqa64       %ymm1, %ymm2{%k1}
+       vmovdqu8        %xmm1, %xmm2{%k1}
+       vmovdqu16       %xmm1, %xmm2{%k1}
+       vmovdqu32       %xmm1, %xmm2{%k1}
+       vmovdqu64       %xmm1, %xmm2{%k1}
+
+       vmovdqa32       (%rax), %ymm2{%k1}
+       vmovdqa64       (%rax), %ymm2{%k1}
+       vmovdqu8        (%rax), %xmm2{%k1}
+       vmovdqu16       (%rax), %xmm2{%k1}
+       vmovdqu32       (%rax), %xmm2{%k1}
+       vmovdqu64       (%rax), %xmm2{%k1}
+
+       vmovdqa32       %ymm1, (%rax){%k1}
+       vmovdqa64       %ymm1, (%rax){%k1}
+       vmovdqu8        %xmm1, (%rax){%k1}
+       vmovdqu16       %xmm1, (%rax){%k1}
+       vmovdqu32       %xmm1, (%rax){%k1}
+       vmovdqu64       %xmm1, (%rax){%k1}
+
+       vmovdqa32       %xmm1, %xmm2{%k1}{z}
+       vmovdqa64       %xmm1, %xmm2{%k1}{z}
+       vmovdqu8        %xmm1, %xmm2{%k1}{z}
+       vmovdqu16       %xmm1, %xmm2{%k1}{z}
+       vmovdqu32       %xmm1, %xmm2{%k1}{z}
+       vmovdqu64       %xmm1, %xmm2{%k1}{z}

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-4.d b/gas/testsuite/gas/i386/x86-64-optimize-4.d
index 10e7b02..18fdeb1 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-4.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-4.d
@@ -9,4 +9,10 @@ Disassembly of section .text:
 
 0+ <_start>:
  +[a-f0-9]+:   a9 7f 00 00 00          test   \$0x7f,%eax
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 fd 28 6f d1       vmovdqa64 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 7f 08 6f d1       vmovdqu8 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 ff 08 6f d1       vmovdqu16 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7e 08 6f d1       vmovdqu32 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 fe 08 6f d1       vmovdqu64 %xmm1,%xmm2
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-4.s b/gas/testsuite/gas/i386/x86-64-optimize-4.s
index 0c4fdce..b6d872d 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-4.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-4.s
@@ -4,3 +4,10 @@
        .text
 _start:
        {nooptimize} testl $0x7f, %eax
+
+       {nooptimize} vmovdqa32  %ymm1, %ymm2
+       {nooptimize} vmovdqa64  %ymm1, %ymm2
+       {nooptimize} vmovdqu8   %xmm1, %xmm2
+       {nooptimize} vmovdqu16  %xmm1, %xmm2
+       {nooptimize} vmovdqu32  %xmm1, %xmm2
+       {nooptimize} vmovdqu64  %xmm1, %xmm2

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.d b/gas/testsuite/gas/i386/x86-64-optimize-5.d
index 085f7f2..012237d 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-5.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d
@@ -106,6 +106,60 @@ Disassembly of section .text:
  +[a-f0-9]+:   62 e1 f5 08 fb c1       vpsubq %xmm1,%xmm1,%xmm16
  +[a-f0-9]+:   62 b1 f5 00 fb c9       vpsubq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:   62 b1 f5 00 fb c9       vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 fd 28 6f d1       vmovdqa64 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 7f 08 6f d1       vmovdqu8 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 ff 08 6f d1       vmovdqu16 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7e 08 6f d1       vmovdqu32 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 fe 08 6f d1       vmovdqu64 %xmm1,%xmm2
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.s b/gas/testsuite/gas/i386/x86-64-optimize-5.s
index 6b4ff10..9756ae8 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-5.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.s
@@ -4,3 +4,10 @@
 
        {evex} vandnpd %zmm1, %zmm1, %zmm5
        {evex} vandnpd %ymm1, %ymm1, %ymm5
+
+       {evex} vmovdqa32        %ymm1, %ymm2
+       {evex} vmovdqa64        %ymm1, %ymm2
+       {evex} vmovdqu8         %xmm1, %xmm2
+       {evex} vmovdqu16        %xmm1, %xmm2
+       {evex} vmovdqu32        %xmm1, %xmm2
+       {evex} vmovdqu64        %xmm1, %xmm2

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.d b/gas/testsuite/gas/i386/x86-64-optimize-6.d
index 0d52c8f..aca119e 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-6.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d
@@ -106,6 +106,60 @@ Disassembly of section .text:
  +[a-f0-9]+:   62 e1 f5 08 fb c1       vpsubq %xmm1,%xmm1,%xmm16
  +[a-f0-9]+:   62 b1 f5 00 fb c9       vpsubq %xmm17,%xmm17,%xmm1
  +[a-f0-9]+:   62 b1 f5 00 fb c9       vpsubq %xmm17,%xmm17,%xmm1
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 f9 6f d1             vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c5 fa 6f d1             vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 79 6f e3          vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c4 41 7a 6f e3          vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 6f 50 7f          vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7d 6f e3          vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c4 41 7e 6f e3          vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 6f 50 7f          vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 fd 28 6f d1       vmovdqa64 %ymm1,%ymm2
+ +[a-f0-9]+:   62 f1 7f 08 6f d1       vmovdqu8 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 ff 08 6f d1       vmovdqu16 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 7e 08 6f d1       vmovdqu32 %xmm1,%xmm2
+ +[a-f0-9]+:   62 f1 fe 08 6f d1       vmovdqu64 %xmm1,%xmm2
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.s b/gas/testsuite/gas/i386/x86-64-optimize-6.s
index 70ccbc4..7c403fc 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-6.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.s
@@ -6,3 +6,10 @@
 
        {evex} vandnpd %zmm1, %zmm1, %zmm5
        {evex} vandnpd %ymm1, %ymm1, %ymm5
+
+       {evex} vmovdqa32        %ymm1, %ymm2
+       {evex} vmovdqa64        %ymm1, %ymm2
+       {evex} vmovdqu8         %xmm1, %xmm2
+       {evex} vmovdqu16        %xmm1, %xmm2
+       {evex} vmovdqu32        %xmm1, %xmm2
+       {evex} vmovdqu64        %xmm1, %xmm2

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-8.d b/gas/testsuite/gas/i386/x86-64-optimize-8.d
new file mode 100644 (file)
index 0000000..46efa52
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-8.d
@@ -0,0 +1,12 @@
+#as: -O2 -march=+noavx
+#objdump: -drw
+#name: x86-64 optimized encoding 8 with -O2
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:   62 f1 7d 28 6f d1       vmovdqa32 %ymm1,%ymm2
+#pass

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-8.s b/gas/testsuite/gas/i386/x86-64-optimize-8.s
new file mode 100644 (file)
index 0000000..4b9865a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-8.s
@@ -0,0 +1,6 @@
+# Check 64bit instructions with optimized encoding
+
+       .allow_index_reg
+       .text
+_start:
+       vmovdqa32       %ymm1, %ymm2

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d3f6bdc..21d3448 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/24348
+       * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
+       vmovdqu16, vmovdqu32 and vmovdqu64.
+       * i386-tbl.h: Regenerated.
+
 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 
        * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1194dcd..26a68d8 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3709,11 +3709,11 @@ vmovd, 2, 0x666E, None, 1, CpuAVX512F, D|Modrm|EVex=2|VexOpcode=0|Disp8MemShift=
 
 vmovddup, 2, 0xF212, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM }
 
-vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vmovntdq, 2, 0x66E7, None, 1, CpuAVX512F, Modrm|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
-vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vmovhlps, 3, 0x12, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
 vmovlhps, 3, 0x16, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
@@ -4190,8 +4190,8 @@ kshiftrq, 3, 0x6631, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=2|No_bSu
 
 vdbpsadbw, 4, 0x6642, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 
-vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vpabsb, 2, 0x661C, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vpmaxsb, 3, 0x663C, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 81575df..bd33eb5 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -60123,7 +60123,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+      2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
          0, 0 } },
@@ -60139,7 +60139,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
          0, 0 } },
@@ -60155,7 +60155,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
          0, 0 } },
@@ -60171,7 +60171,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+      2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
          0, 0 } },
@@ -63555,7 +63555,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
          0, 0 } },
@@ -63571,7 +63571,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+      2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
          0, 0 } },