drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 28 Apr 2022 04:19:24 +0000 (21:19 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 29 Apr 2022 21:30:21 +0000 (14:30 -0700)
Compute engines have a separate register that the driver should use to
perform MMIO-based TLB invalidation.

Note that the term "context" in this register's bspec description is
used to refer to the engine instance (in the same way "context" is used
on bspec 46167).

Bspec: 43930
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220428041926.1483683-3-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_gt.c
drivers/gpu/drm/i915/gt/intel_gt_regs.h

index 92394f1..53307ca 100644 (file)
@@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
                [VIDEO_DECODE_CLASS]            = GEN12_VD_TLB_INV_CR,
                [VIDEO_ENHANCEMENT_CLASS]       = GEN12_VE_TLB_INV_CR,
                [COPY_ENGINE_CLASS]             = GEN12_BLT_TLB_INV_CR,
+               [COMPUTE_CLASS]                 = GEN12_COMPCTX_TLB_INV_CR,
        };
        struct drm_i915_private *i915 = gt->i915;
        struct intel_uncore *uncore = gt->uncore;
index a39718a..a0a49c1 100644 (file)
 #define GEN12_VD_TLB_INV_CR                    _MMIO(0xcedc)
 #define GEN12_VE_TLB_INV_CR                    _MMIO(0xcee0)
 #define GEN12_BLT_TLB_INV_CR                   _MMIO(0xcee4)
+#define GEN12_COMPCTX_TLB_INV_CR               _MMIO(0xcf04)
 
 #define GEN12_MERT_MOD_CTRL                    _MMIO(0xcf28)
 #define RENDER_MOD_CTRL                                _MMIO(0xcf2c)